Member of Technical Staff — Accelerator Systems

RadixArk•Palo Alto, CA

9d•Hybrid

About The Position

RadixArk is seeking a Member of Technical Staff: Accelerator Systems to push the limits of performance for frontier AI systems. Most performance engineering assumes a single vendor's stack. This role assumes none. You'll bring up, optimize, and maintain SGLang, Miles, and the RadixArk infrastructure stack across NVIDIA and AMD GPUs, Google TPUs, modern server CPUs, and a growing set of emerging AI accelerators. That means porting kernels and runtimes onto unfamiliar hardware, designing the abstractions that keep one codebase fast on all of it. You will be working directly with silicon and our partners, often on pre-release platforms with immature tooling. This is one of the broadest technical roles at RadixArk. The problem changes shape with every new platform: a memory hierarchy that punishes your last set of assumptions, a compiler that fuses differently, a collective library that doesn't exist yet. We're looking for engineers who find that appealing rather than exhausting, and who can go deep on a new architecture fast without losing the performance instincts they built on the last one.

Requirements

4+ years of experience in systems, performance, or ML infrastructure engineering
Deep expertise in at least one accelerator programming model (CUDA, ROCm/HIP, Pallas/XLA, Triton, or a vendor SDK), with demonstrated ability to pick up new ones quickly.
Strong understanding of accelerator architecture: memory hierarchy, bandwidth limits, occupancy, and the tradeoffs between them
Experience writing or optimizing high-performance kernels for ML workloads
Experience with distributed execution and communication libraries (NCCL, RCCL, MPI, or equivalents)
Proficiency in C++ and Python
Strong debugging and profiling skills at the system level, including on platforms where the tooling is incomplete or unreliable
Track record of performance work that shipped into production

Nice To Haves

Experience bringing up ML workloads on new silicon.
Hands-on depth in more than one vendor ecosystem
Experience with compiler stacks (XLA, MLIR, TVM, Triton) or building compiler passes and IR transformations
Experience designing hardware abstraction layers or portable kernel interfaces
Quantization and mixed-precision work across differing numeric formats and hardware support levels
Experience with distributed inference systems (SGLang, vLLM) or training/RL frameworks (Miles, Megatron, veRL, TorchTitan)
CPU inference optimization (AVX-512/AMX, oneDNN, NUMA-aware execution)
Experience optimizing collective communication at scale, or scaling workloads to 1000+ accelerators
Contributions to kernel, compiler, or ML systems open source
Direct collaboration with silicon vendors or cloud partners on technical evaluations
Background in HPC or other performance-critical systems

Responsibilities

Bring up RadixArk's inference and training systems on new accelerator platforms and drive them to competitive performance
Design hardware abstractions that let a single codebase stay fast across vendors without forking
Port and optimize kernels across programming models and memory architectures
Build cross-platform benchmarking, profiling, and regression detection so performance claims hold up on every target
Debug numerical divergence and correctness gaps between platforms
Work with vendor engineering teams on pre-release hardware, compiler and driver issues, and roadmap feedback
Partner with kernel, runtime, distributed systems, and product engineers to land performance wins end to end
Serve as the internal source of truth on what each platform is actually good at
Contribute hardware-specific optimizations, benchmarks, and portability work back to open-source SGLang and Miles