Machine Leaning Performance Engineer (Inference)

Tower Research Capital • New York, NY

13h • $200,000 - $300,000 • Hybrid

About The Position

As part of Tower Research's Core Engineering team, you will bridge the gap between quantitative research and high-performance production systems, architecting inference pipelines that operate at the physical limits of hardware. Your objective will be to drive the speed, efficiency, and reliability of our ML inference pipelines to their absolute limits, ensuring our predictive models consistently achieve microsecond-level latency.

Requirements

• 2+ years of experience optimizing deep learning inference in latency-sensitive or high-throughput production environments, in any domain.
• Deep expertise in lower-level ML framework development (PyTorch/JAX), paired with strong Python/C++ skills and a thorough understanding of mixed-precision computation.
• Proven experience in custom GPU kernel development.
• Deep familiarity with advanced optimization libraries and compilers (e.g., Triton, TensorRT, ONNX, IREE, HLS4ML, cuBLAS, CUTLASS) as well as profiling tools (e.g., Nsight Systems, Nsight Compute).
• Deep expertise in GPU microarchitecture, encompassing SM execution, warp scheduling, and full memory hierarchy optimization (registers to HBM).
• Proven record of rigorous, data-driven approach to evaluating inference performance across heterogeneous compute architectures.

Nice To Haves

• Practical experience targeting and optimizing inference workloads on specialized hardware ecosystems, including FPGAs and ASICs.
• Prior experience in financial trading is not required.

Responsibilities

• Lead the technical evaluation of diverse inference platforms - ranging across CPUs, GPUs, and FPGAs - to guide Tower's infrastructure deployment decisions.
• Analyze and enhance execution across deep memory hierarchies to maximize resource utilization and parallel processing. You will assess and resolve memory subsystem and interconnect bottlenecks across the end-to-end inference lifecycle.
• Collaborate with Infrastructure teams to understand thermal, power, and operational constraints of hardware platforms to design inference strategies for our latency-critical trading strategies that fit within those envelopes.
• Develop highly optimized kernels and integrate specialized performance libraries to extract maximum computational throughput from the underlying silicon.
• Implement advanced model reduction techniques (quantization, pruning, distillation) to ensure compact memory footprints and numerical stability. Prioritize optimization for low-latency, event-level inference workloads to meet real-time trading requirements.
• Collaborate closely with ML Researchers, HPC Engineers, FPGA Engineers, and Datacenter Engineers to bring to fruition target deployments.

Benefits

• Generous paid time off policies
• Savings plans and other financial wellness tools available in each region
• Hybrid working opportunities
• Free breakfast, lunch, and snacks daily
• In-office wellness experiences and reimbursement for select wellness expenses (e.g., gym, personal training and more)
• Company-sponsored sports teams and fitness events (JPM Corporate Challenge, Cycle for Survival, Wall Street Rides FAR and more)
• Volunteer opportunities and charitable giving
• Social events, happy hours, treats, and celebrations throughout the year
• Workshops and continuous learning opportunities

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Education Level: No Education Listed