Logic Design Engineer

Intel Corporation•Santa Clara, CA

3d•$220,920 - $311,890•Hybrid

About The Position

Intel is shaping the future of technology to help create a better future for the entire world. Our work in pushing forward fields like AI, analytics, and cloud-to-edge technology is at the heart of countless innovations. With a career at Intel, you'll have the opportunity to use technology to power major breakthroughs and create enhancements that improve our everyday quality of life. Join us and help make the future more wonderful for everyone. Intel's multiprotocol SerDes design team is hiring for a critical design position in Santa Clara office to ensure continued support of some of the world's most versatile next-generation products. We have a long track record of silicon success over multiple technology nodes. Supporting multi-national High speed SerDes team, we are hiring a technically experienced Logic Design Engineer.

Requirements

Minimum 5+ years of experience in Mixed signal design specifically High Speed SerDes design and architecture
Detailed knowledge of SerDes PMA and PCS layers
Experienced with post-silicon validation and support of the High Speed SerDes IP
Reading and interpreting technical specs to come up with Microarchitecture and implement RTL design in System Verilog.
Computer system architecture and Digital Design.
OVM/UVM methodology to interact with the Validation designers for Val content development.

Nice To Haves

Experience with automated Place-and-route (APR) team to convey constraints and work together to close timing issues
Scripting in at least one of the following interpreted language (e.g. TCL, Perl, Python, Ruby)

Responsibilities

Logic design of High Speed SerDes Design, register transfer level (RTL) coding, and simulation for an IP required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs.
Participating in the definition of architecture and microarchitecture features of the block being designed.
Applying various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.
Reviewing the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.
Supporting SoC customers to ensure high quality integration and verification of the IP block.
Driving quality assurance compliance for smooth IP SoC handoff.