This R&D engineer role is part of the timing optimization group of Cadence’s Innovus Place & Route product. This key Innovus R&D group is responsible for optimizing timing (how fast a chip functions) and power (the power consumption of the chip), and the timing closure flow. The Innovus product is a key product used by a variety of chip manufacturing companies such as mobile, automotive, CPU & GPU cores, & AI. The work done in this high-performance team has a huge impact on the chip industry and products that are used in our daily lives. We are looking for talented candidates with a strong background in electronic design automation (timing, power analysis, optimization), and excellent software engineering skills, experience with multithreaded and distributed optimization. We are looking for individuals that can make the next breakthrough in the technology that we provide to the customers, making a big impact to the industry.
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Job Type
Full-time
Career Level
Senior