Lead Principal Engineer Analog Design

Infineon•Morrisville, NC

9d•$192,200 - $264,300•Onsite

About The Position

As a Lead Principal Engineer Analog Design on our Research & Development team, you'll have the opportunity to merge creativity with your technical expertise by shaping the future of technology, driving groundbreaking projects, and bringing new ideas to life.

Requirements

BS, MS, or PhD in Electrical Engineering or Physics
5 years in technical leadership positions
Significant experience in DC-DC control and Power IC development
Methodical, data-driven problem solving
Clear, concise communications and collaborative partner who proactively syncs with coworkers
Curious and fast learner, Innovative mindset
Customer/impact oriented

Responsibilities

Lead a small team of IC Design Engineers and develop talented individuals for technical and career growth
Design/verify DC-DC control loops; compensation, transient response, EMI/EMC, efficiency optimization
High voltage device handling (BCD processes), gate drivers, synchronous rectification, current sensing
SPICE simulations (DC/AC/transient/noise), stability/Bode analysis for control loops, PSRR/CMRR
PVT corners and Monte Carlo (mismatch/yield) with sensitivity analysis; parasitic-aware sims post layout
Behavioral modeling (Verilog A/MATLAB) for speed and architecture exploration; back annotation and correlation. Layout collaboration and physical verification
Interpret DRC, LVS, PEX; assist with floor-planning, device sizing, resistor/cap selection; basic EM/IR checks
Incorporate ESD/latch up constraints and reliability rules for the target process (often CMOS/BCD for power)
Integrate blocks into chip/top level: biasing, references, I/O paring/ESD, power domains, startup/reset sequencing
Support ATE/test engineering with characterization vectors and limit setting; contribute to yield/ramp investigations.
Work with Systems/Applications to translate requirements to circuit specs; with Reliability/Quality on stress/aging (BTI/HCI/EM)considerations; with Packaging on parasitic/thermal; with Test/Production, DfT and test time; with Technology Development on Si process improvements