Lead Photonics Integrated Circuit Engineer

Terra Quantum•San Francisco, CA

4d•Remote

About The Position

The Lead Photonics & Quantum Integration will own the technical strategy, execution, and roadmap appendices covering photonic interconnect, integrated silicon photonics, single-photon source integration, and longer-horizon quantum–classical hybrid compute elements within the programme’s technology roadmap. The successful candidate will bridge deep expertise in quantum photonics device physics with the practical demands of semiconductor process integration, working closely with the device teams to identify co-integration opportunities on the shared hardware platform. As a senior photonics engineer you will take ownership of the physical design and verification of cutting-edge photonic integrated circuits (PICs), guiding designs from initial proof-of-concept phases to high-volume manufacturing readiness.

Requirements

PhD in Physics, Electrical Engineering, or a closely related discipline with a focus on photonics, quantum optics, or integrated photonic devices.
Deep technical understanding of advanced node semiconductor fabrication, sophisticated automation capabilities and knowledge of high-density chip design.
Demonstrated track record in experimental quantum photonics R&D, including design, fabrication liaison, and characterisation of photonic devices or circuits.
Deep knowledge of semiconductor process flows (CMOS front-end and back-end) and an understanding of how photonic elements integrate within or alongside electronic process modules.
Understanding of analog circuit layout, Silicon Photonic constraints, and device physics within advanced sub-micron CMOS and SiPh technologies.
Experience translating research-stage photonic technologies toward manufacturable, scalable hardware — ideally within a commercial or national-lab R&D environment.
Strong publication record and the ability to communicate complex photonic and quantum concepts to cross-disciplinary engineering teams.
Proficiency in physical modelling and data analysis (C++, Python, SKILL, TCL, HDL, MATLAB, or equivalent); familiarity with photonic simulation tools (Lumerical, COMSOL, MEEP, or similar).
Experience with Cadence Virtuoso (Custom Layout, SDL) and industry-standard verification suites (Calibre, Hercules, ICV, Dracula, or Primeyield)
Experience developing or contributing to multi-year technology roadmaps, including milestone definition, risk assessment, and cost estimation.

Responsibilities

Lead the Photonics technology roadmap aligned with the programme’s overall progression.
Define go/no-go decision criteria, risk registers, and cost models for photonic integration at each process node, consistent with the programme’s existing MPW and pilot-line budgeting methodology.
Conduct technology horizon scanning and competitive landscape analysis across silicon photonics, photonic quantum computing, and optical interconnect for AI accelerators.
Lead the design, simulation, and characterisation of photonic components (waveguides, modulators, photodetectors, single-photon sources) compatible with the programme’s FEOL + X + BEOL process flow.
Lead complex, full-loop manual and automated layout designs and mixed-signal functions (high-speed/general I/Os, ESD structures).
Drive the full tape-out process, including floor planning, waveguide routing, and mask data preparation.
Design and simulate photonic integrated circuits for communication, sensing, or compute-related applications.
Work with fabrication partners to develop layouts and ensure manufacturable designs.
Collaborate with electronics, packaging, and test teams to integrate PICs into larger hardware systems.
Execute rigorous post-layout verification (DRC, LVS, fill, density) across multiple stepping versions.
Trace defect sources, mitigate layout-dependent issues, and ensure DRC/LVS cleanliness prior to tape-out.
Evaluate and specify co-integration pathways for photonic elements with the existing HZO ferroelectric and metal-oxide layers, identifying shared ALD and BEOL metal-stack process steps.
Develop optical test and characterisation methodologies from wafer-level through to packaged sub-assembly, defining pass/fail metrics for manufacturing readiness.
Establish and own the photonics simulation workflow, interfacing with the programme’s existing layered tool chain.
Develop compact models and Verilog-A behavioural descriptions for photonic devices to enable system-level co-simulation with the NC-FET/memristor fabric.
Model optical interconnect power, latency, and bandwidth budgets for hybrid electronic–photonic accelerator architectures.
In time build and lead a small specialist team as the photonics workstream scales through programme phases.
Manage relationships with foundry partners, MPW brokers, and academic collaborators for photonic process access and IP development.
Represent the programme at conferences, review panels, and in publications; contribute to grant and funding applications.
Participate in programme-wide design reviews, providing photonics perspective on hybrid systolic/crossbar architecture decisions, precision formats, and KV-cache strategies.
Contribute to the programme’s future framework, specifically on optical compute and interconnect as an enabling pillar.