Lead Functional Product Engineer, Power Analysis

Cadence Design Systems•San Jose, CA

9d•$114,800 - $213,200•Onsite

About The Position

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. We are looking for a skilled engineer to join our Power Analysis team, focused on developing, debugging, and deploying Signoff power analysis flows at customer environments.

Requirements

Hands-on experience with Signoff power analysis (static and dynamic power)
Knowledge of power optimization techniques in Synthesis (clock gating, operand isolation, multi-Vt cell selection)
Working knowledge of UPF (Unified Power Format) — power domains, isolation, level shifting, retention
Proficiency in Verilog/SystemVerilog for design analysis and testcase creation
Understanding of digital design fundamentals — clock domains, pipeline stages, timing/power trade-offs
Experience with low-power design methodologies (DVFS, power gating, multi-voltage)
Familiarity with Liberty (.lib) and SPEF formats
Scripting skills: Tcl, Python, or Shell
Familiarity with tools such as Joules, Voltus, PTPX or equivalent
B.E./B.Tech or M.E./M.Tech in Electronics / VLSI / Computer Engineering or equivalent
3+ years of industry work experience

Responsibilities

Closely work with R&D to develop and maintain Signoff power analysis flows including integration with synthesis and PnR stages
Reproduce, debug, and resolve customer-reported issues in power analysis tools and flows
Deploy and validate power analysis tools at customer sites; provide hands-on technical support
Collaborate with customers to optimize power results and improve flow efficiency
Contribute to flow automation and scripting for repeatable deployments
Document debug findings, best practices, and flow guidelines