Lead Firmware Engineer - Power Conversion Control

Proper Voltage•Carlsbad, CA

14h•$150,000 - $175,000•Onsite

About The Position

Proper Voltage designs and builds safety-critical battery energy storage systems. This role leads the real-time control firmware for our bidirectional DC/DC power conversion stage — the code that closes current and voltage loops on multiphase interleaved converters, arbitrates operating modes, and commands a safe state when a fault occurs. This is not a general embedded role that happens to touch PWM. You will implement compensators within a sub-microsecond ISR budget with correct fixed-point scaling and correct ADC-to-PWM trigger phasing, then prove on the bench that the hardware does what the design says it should. You will work as a pair with our Lead Controls Engineer – Power Electronics. They own what the loop should do and why; you own how it runs on the silicon. You know enough control theory to implement their design faithfully, push back when it costs more cycles than the budget allows, and tell them what the silicon actually delivers. You will lead implementation within our portable, MCU-agnostic DC/DC control library.

Requirements

BS in Electrical Engineering, Computer Engineering, or equivalent demonstrated capability.
Six or more years developing production embedded firmware in C for resource-constrained real-time systems.
Production control firmware on switched-mode power converters, inverters, or motor drives. You can name the topology, control mode, switching and sampling frequencies, and ISR budget for a converter whose control firmware you implemented and brought up on hardware.
Working knowledge of control fundamentals: PID and 2p2z/3p3z difference equations, discretization basics, how sampling and computational delay reduce phase margin, and saturation and anti-windup — enough to implement a controls engineer's design faithfully and recognize when the implementation changes its behavior.
Fluency with the peripherals that make digital power work: high-resolution PWM, PWM-triggered ADC with programmable sample instants, analog comparators and DACs for fast fault paths, and DMA.
Fixed-point arithmetic competence — Q-format scaling, range and overflow analysis, saturating behavior — and the ability to justify a fixed-point versus floating-point decision on execution-time grounds.
Deterministic ISR design under hard timing constraints, including the ability to measure and defend worst-case execution time rather than estimate it.
Independent lab capability on live power hardware with oscilloscopes, isolated and differential probes, current probes, electronic loads, and bidirectional supplies.
Version control, code review, and a demonstrated track record of writing specifications and test evidence, not only code.

Nice To Haves

dsPIC experience (significant advantage)
Production firmware on dsPIC33C, dsPIC33CK, or dsPIC33CH digital signal controllers for power conversion, including high-resolution PWM generators with PCI-based synchronization, dedicated and shared ADC core configuration, early interrupt generation, alternate working register sets, DSP MAC instruction use in compensator inner loops, and MPLAB X / XC16 toolchain depth.
Familiarity with Microchip's digital power reference ecosystem — Digital Power Development Board, Digital Power Plug-In Modules, and the PowerSmart Digital Control Library Designer.
Bidirectional and multiphase interleaved converter control, including current sharing and phase balancing between paralleled phases.
Average current mode control implementation specifically, as distinct from voltage mode or peak current mode.
Wide-bandgap power stages (GaN, SiC) and the firmware-visible consequences of fast switching edges — sense chain noise, blanking, dead-time sensitivity, and gate-drive fault behavior.
ARM Cortex-M devices with advanced timer peripherals in addition to dsPIC; we value portability across both architectures.
Running firmware control code inside PLECS or MATLAB/Simulink (C-Script, DLL, or S-function blocks) for software-in-the-loop verification.
Hands-on loop gain measurement with a network or frequency response analyzer.
Battery energy storage, EV charging, photovoltaic inverter, or grid-interactive converter experience, including charge profile management and BMS interaction such as current limit negotiation, precharge, and contactor sequencing.
Functional safety and certification exposure: IEC 61508 or ISO 26262 concepts, UL 1973, UL 1998, UL 9540, FMEA/FMEDA, and software safety requirements traceability.
MISRA C, static analysis, on-target unit testing, and hardware- or processor-in-the-loop infrastructure.
CAN and CANopen, and firmware update over an embedded bus.
Contributions to reusable, portable control libraries with clean hardware abstraction, as opposed to one-off application firmware.

Responsibilities

Real-time control loop implementation for four-switch buck-boost power stages and successor topologies, including multiphase interleaved operation and phase current balancing.
Modules within the portable DC/DC control library: compensator implementations, mode arbitration, scheduler and ISR architecture, and the platform abstraction layer.
Converter protection firmware — cycle-by-cycle current limit, overvoltage and undervoltage, thermal derating, gate-drive fault handling, and safe-state transitions.
Implementation verification: evidence that firmware matches the control design, plus measured timing, jitter, and worst-case execution time.
Firmware verification evidence supporting UL 1973, UL 1998, and UL 9540 certification.
Implement compensators and control loops in C from the controls engineer's specifications, to fixed cycle budgets using fixed-point or single-precision arithmetic as appropriate, with explicit saturation, anti-windup, and bumpless mode transfer.
Verify each implementation against the control model by running the firmware control code in closed-loop simulation and comparing its response to the reference within a defined tolerance.
Architect and maintain the control ISR and scheduler — fast control task and slower supervisory task — with deterministic timing, measured jitter, and documented worst-case execution time.
Configure and validate the PWM, ADC, comparator, and DAC trigger architecture, including sampling instant placement relative to switching noise, trigger-to-response latency, dead-time, and hardware-independent cycle-by-cycle protection paths.
Measure sampling delay, computational delay, and PWM update latency on target, and feed them back to the controls engineer so the design's delay budget reflects the real silicon.
Implement operating mode arbitration: constant current, constant voltage, constant power, current limit, soft-start, buck-to-boost transition, phase shedding, and charge/discharge direction reversal.
Implement converter protection firmware and safe-state transitions to the thresholds and response times set by the control and hardware specifications.
Bring up new converter hardware in the lab, from first switching event through full envelope characterization, including gate-drive debug, dead-time optimization, and shoot-through avoidance.
Support loop gain measurement by network analyzer injection, step-load transient response, and efficiency testing with the controls engineer, and debug discrepancies between model and hardware.
Build and maintain on-target unit tests and hardware-in-the-loop regression sufficient to catch control regressions before hardware.
Author firmware specifications and verification evidence to a standard that withstands certification-body review.
Serve as technical lead for power conversion firmware: review control and embedded code written by others, and contribute to hardware design reviews covering the sense chain, ADC architecture, and protection paths.