At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. This role involves leading cutting-edge electrical and functional validation for next-generation DDR interfaces such as DDR5, LPDDR5, LPDDR6, HBM4 and GDDR7. The engineer will design and execute innovative testing strategies to accelerate post-silicon bring-up, transform raw data into actionable insights through advanced analysis and visualization, and resolve complex issues by driving JIRA-based debug workflows and collaborating across teams. The position requires delivering high-impact characterization reports that influence product decisions and customer success, and automating processes using Python for validation, data processing, and reporting. The successful candidate will also serve as the go-to expert for customer DDR IP challenges, ensuring rapid debug and world-class technical support. Cadence is a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable customers to create revolutionary products and experiences. Cadence has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For.
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Job Type
Full-time
Career Level
Senior