Lead Design Engineer

Cadence Systems • Austin, TX

2d

About The Position

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Requirements

• B.E./B.Tech or M.Tech/M.S. in Electronics, VLSI, or related field
• 4–7 years of hands-on DV experience in semiconductor/ASIC/SoC companies

Responsibilities

• Define the overall verification strategy, including the choice of methodology (typically UVM/SystemVerilog), tools, and infrastructure.
• Design scalable, reusable, and robust verification environments. This includes developing Bus Functional Models (BFMs), monitors, scoreboards, and checkers.
• Analyze architectural specifications to identify critical features and corner cases that require rigorous testing.
• Write complex test cases and sequences to achieve high functional coverage.
• Lead the root-cause analysis of complex design bugs, collaborating closely with design engineers to implement fixes.
• Implement constrained-random stimulus generation to explore the design space beyond directed tests.
• Utilize formal tools to prove specific properties or find deep-seated bugs that simulation might miss.
• Monitor and analyze functional and code coverage metrics.
• Oversee simulations on the synthesized netlist to verify timing and reset behavior.
• Define the "definition of done" and provide final technical approval for the verification phase.
• Guiding junior engineers on coding standards and debugging techniques.
• Acting as the primary technical point of contact between the design, architecture, and emulation teams.
• Managing timelines, identifying risks in the verification schedule, and prioritizing tasks to meet project deadlines.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior