Lead Design Engineer

Cadence SystemsSan Jose, CA
Onsite

About The Position

Lead cutting-edge electrical and functional validation for next-generation DDR interfaces such as DDR5, LPDDR5, LPDDR6, HBM4 and GDDR7. Design and execute innovative testing strategies to accelerate post-silicon bring-up. Transform raw data into actionable insights through advanced analysis and visualization. Resolve complex issues by driving JIRA-based debug workflows and collaborating across teams. Deliver high-impact characterization reports that influence product decisions and customer success. Automate using Python for validation, data processing, and reporting. Be the go-to expert for customer DDR IP challenges, ensuring rapid debug and world-class technical support.

Requirements

  • M. Tech + 4 years’ experience or B. Tech with 6 years’ experience

Responsibilities

  • Lead cutting-edge electrical and functional validation for next-generation DDR interfaces
  • Design and execute innovative testing strategies to accelerate post-silicon bring-up
  • Transform raw data into actionable insights through advanced analysis and visualization
  • Resolve complex issues by driving JIRA-based debug workflows and collaborating across teams
  • Deliver high-impact characterization reports that influence product decisions and customer success
  • Automate using Python for validation, data processing, and reporting
  • Be the go-to expert for customer DDR IP challenges, ensuring rapid debug and world-class technical support

Benefits

  • bonus
  • equity
  • paid vacation
  • paid holidays
  • 401(k) plan with employer match
  • employee stock purchase plan
  • a variety of medical, dental and vision plan options
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