Junior FPGA Developer

Edgehog Trading • Chicago, IL

7d • $100,000 - $175,000 • Onsite

About The Position

We are seeking a Junior FPGA Developer to join our team. In this role, you will be responsible for designing, implementing, and verifying RTL logic in Verilog or SystemVerilog, specifically for ultra-low-latency trading applications. You will develop simulation testbenches and functional verification environments to ensure designs are validated before hardware deployment. Collaboration with senior FPGA engineers and the trading infrastructure team is key to understanding and implementing latency requirements. You will also be involved in the synthesis, place-and-route, and static timing analysis processes, iterating on designs to meet strict timing constraints. Additionally, you will participate in hardware bring-up and on-board debugging, utilizing waveform analysis and other diagnostic tools. A unique aspect of this role is the use of AI tools to accelerate the development workflow, including RTL review, testbench generation, debugging, and documentation. You will also grow your understanding of market data protocols such as Ethernet, PCIe, and exchange feed formats as they relate to the systems you build.

Requirements

• BS or MS in Electrical Engineering, Computer Engineering, or a related field
• Hands-on experience with RTL design in Verilog or SystemVerilog — coursework, personal projects, or internship experience all count
• Familiarity with FPGA simulation tools (e.g., ModelSim, QuestaSim, Vivado, Quartus) and the synthesis-to-deployment flow
• Understanding of digital logic fundamentals: state machines, FIFOs, clock domain crossing, timing constraints
• Comfort working in a Linux environment
• Ability and eagerness to incorporate AI tools into your development and debugging workflow
• A strong desire to learn the HFT domain — no prior finance knowledge required
• Strong analytical instincts: when something behaves unexpectedly in hardware, you dig until you find it

Nice To Haves

• Python, basic C or C++ is a plus

Responsibilities

• Design, implement, and verify RTL logic in Verilog or SystemVerilog targeting ultra-low-latency trading applications
• Develop simulation testbenches and functional verification environments to validate FPGA designs before hardware deployment
• Work closely with senior FPGA engineers and the trading infrastructure team to understand latency requirements and translate them into hardware design decisions
• Run synthesis, place-and-route, and static timing analysis; iterate on designs to meet strict timing constraints
• Participate in hardware bring-up and on-board debugging, using waveform analysis and other diagnostic tools
• Use AI tools to accelerate your development workflow — RTL review, testbench generation, debugging, and documentation
• Grow your understanding of market data protocols (Ethernet, PCIe, exchange feed formats) as they relate to the systems you build

Benefits

• Comprehensive health, dental, and vision insurance with premiums 100% covered by the firm
• 401(k) with a 4% company match
• Unlimited paid time off and sick leave
• Free lunch, coffee, drinks, and snacks
• Commuter benefits
• Monthly happy hours and annual team events

What This Job Offers

• Job Type: Full-time
• Career Level: Entry Level