Intern - PHY Digital Design & Automation Engineer, HBM

Micron Technology • Richardson, TX

1d

About The Position

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Heterogeneous Integration Group (HIG) HBM Architecture team develops future High-Bandwidth Memory (HBM) architectures, PHY design methodologies, and automation solutions that enable next-generation AI, high-performance computing, networking, and data center applications. The team works closely with Architecture, Design Engineering, Verification, Product Engineering, and external partners to advance memory technologies while improving design quality, productivity, and development efficiency.

As a Senior or Graduate Engineering Intern, you will collaborate with experienced HBM architects and engineers to support the development of digital design methodologies, automation frameworks, timing analysis flows, and architecture validation solutions for next-generation HBM PHY and IO subsystems. This role offers hands-on experience in digital design, verification, automation, and timing analysis, while providing opportunities to leverage AI Assisted engineering workflows, Large Language Models (LLMs), and Generative AI tools to enhance engineering productivity and design efficiency.

Requirements

• Currently pursuing a Master's or Ph.D. degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
• Demonstrated understanding of digital design concepts including finite state machines (FSMs), pipelining, clock-domain crossing (CDC), timing analysis, and computer architecture.
• Experience with RTL design and verification concepts using Verilog or SystemVerilog.
• Proficiency in Python, C++, or a comparable programming language, and experience working in Linux-based development environments.
• Strong analytical, debugging, problem-solving, written communication, and verbal communication skills.

Nice To Haves

• Experience with digital implementation flows, static timing analysis (STA), timing closure methodologies, and timing constraint development.
• Familiarity with UVM-based verification environments and regression infrastructure development.
• Experience using EDA tools from Cadence, Synopsys, Siemens, or equivalent vendors.
• Exposure to automation, software development, data analytics, AI Assisted workflows, Large Language Models (LLMs), or Generative AI-based productivity solutions.
• Coursework, research, or project experience related to VLSI design, digital systems, computer architecture, memory systems, timing analysis, or mixed-signal design environments.

Responsibilities

• Support digital design, integration, and timing analysis activities for HBM PHY and IO subsystems, including timing constraint development and timing closure efforts.
• Develop and implement verification solutions using Verilog/SystemVerilog and UVM-based environments, analyze simulation results, and debug functional or timing-related issues.
• Create Python-based automation tools and AI Assisted engineering workflows that leverage Large Language Models (LLMs) and Generative AI technologies to improve engineering efficiency.
• Collaborate with architecture, design, verification, and product engineering teams to evaluate features, validate architectures, and improve design quality metrics.
• Document technical findings and present results through design reviews, engineering discussions, and project presentations.

Benefits

• Choice of medical, dental and vision plans
• Benefit programs that help protect your income if you are unable to work due to illness or injury
• Paid family leave
• Robust paid time-off program
• Paid holidays

What This Job Offers

• Career Level: Intern