Ayar Labs is hiring a graduate intern for its Optical Packaging team, which develops fiber-to-chip interfaces, optical connectors, and assembly processes for the company’s optical I/O chiplets. The intern will analyze optical test data from these interfaces and use it to inform engineering decisions. The work involves insertion-loss and coupling measurements from components, wafers, packaged parts, and supplier data, with the goal of isolating variation sources and identifying component and assembly factors that drive coupling loss. The role combines hands-on laboratory measurement with statistical analysis in Python. Projects will be scoped to the intern’s background and interests. The intern will be mentored by the Optical Packaging team and work alongside test, characterization, and process engineers. The position is on-site in Ayar Labs’ San Jose office for a term from May to August 2027. No immigration support is available except for F1, and relocation support is not provided.
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Career Level
Intern