Intern - DRAM IP Circuits Design Engineer

Micron Technology • Boise, ID

2d

About The Position

The DRAM Engineering Group, IP Development team is responsible for delivering high-quality DRAM Intellectual Property solutions that enable next-generation AI, Mobile, Client, Data Center, and Graphics products. The team develops analog, mixed-signal, and high-speed interface circuits used across Micron’s future memory products, with a focus on predictable execution, design quality, reliability, and innovation across circuit design and verification flows. As an intern, you will work alongside experienced circuit designers to support the development of critical DRAM IP blocks used in upcoming memory solutions. This internship provides hands-on exposure to semiconductor circuit design, simulation, verification, physical design support, silicon validation, and advanced technology development. You will contribute to meaningful engineering projects while gaining experience using widely recognized EDA software, circuit modeling techniques, AI Assisted workflows, and multi-functional processes.

Requirements

• Currently pursuing a Bachelor’s, Master’s, or Ph.D. degree in Electrical Engineering, Computer Engineering, Semiconductor Engineering, or a related STEM field.
• Completed coursework or academic projects in CMOS analog circuits, CMOS digital circuits, semiconductor devices, signal integrity, or related circuit design topics.
• Basic programming experience in Python, Perl, TCL, MATLAB, or similar scripting and analysis languages.
• Demonstrated analytical, problem-solving, communication, and teamwork skills.
• Ability to complete a technical project, summarize results, and present recommendations to engineering partners.

Nice To Haves

• Experience with analog, mixed-signal, memory, high-speed interface, or semiconductor circuit design through coursework, research, internship, or project work.
• Familiarity with industry-standard EDA tools, circuit simulation methodologies, SPICE simulation, Verilog modeling, or mixed-signal verification flows.
• Exposure to physical design concepts such as layout review, parasitic extraction, post-layout simulation, floor-planning, or design rule considerations.
• Experience Applying AI, Using AI, or Employing Artificial Intelligence to improve engineering workflows, automation, data analysis, software development, or user documentation.
• Familiarity with AI Assisted tools, Agentic AI, LLMs, Large Language Models, Generative AI, or AI-Enabled workflows for engineering productivity and design quality improvements.

Responsibilities

• Assist in the design, development, simulation, and optimization of analog, mixed-signal, and high-speed interface circuits for next-generation DRAM IP.
• Perform circuit simulations using SPICE, Verilog, and mixed-signal simulation environments, including analysis across process, voltage, and temperature conditions.
• Support schematic development, design reviews, layout review, parasitic extraction, post-layout verification, and circuit performance validation.
• Collaborate with verification, layout, product engineering, modeling, and multi-functional teams to meet project objectives and improve design quality.
• Develop automation scripts and Agentic AI workflows to improve engineering productivity, design methodology, simulation efficiency, and technical analysis quality.

Benefits

• Choice of medical, dental and vision plans
• Benefit programs that help protect your income if you are unable to work due to illness or injury
• Paid family leave
• Robust paid time-off program
• Paid holidays

What This Job Offers

• Job Type: Full-time
• Career Level: Intern
• Education Level: Ph.D. or professional degree