Intern - Characterization and Support (Fall 2026)

Cadence Systems•San Jose, CA

8d•Onsite

About The Position

This is an on-site internship role in San Jose, California, within the Cadence DDR IP group for a Post-Silicon Validation Engineering Intern. The intern will be responsible for validating both system-level and electrical performance of internal silicon test chips. The role includes debugging silicon issues in close collaboration with analog and digital design teams, and delivering high-quality characterization reports. The intern will work cross-functionally to ensure product functionality, reliability, and successful deployment. The candidate is expected to be strongly motivated by the prospect of driving system and electrical testing efforts for identifying silicon issues and being involved in debug efforts for the same.

Requirements

Currently pursuing a Bachelor's or Master’s degree in electrical engineering.
0-2 years of relevant work experience.
Very good fundamentals in analog and digital electronics, RTL, Signal integrity, control systems.
Strong analytical and problem-solving skills.
Excellent written and verbal communication skills.
Ability to work collaboratively in a team environment.
Candidate should be able to prove they can work fulltime hours in San Jose during the Fall.
Must have legal authorization to work in the US.

Nice To Haves

Prior experience in the hardware semiconductor or electronics industry is a plus.
Experience with script-based test automation in Python, C or other scripting tools is a plus.
As this role is expected to be employed in San Jose during the Fall semester, applicants should ideally be attending a local school.

Responsibilities

Validating both system-level and electrical performance of internal silicon test chips.
Debugging silicon issues in close collaboration with analog and digital design teams.
Delivering high-quality characterization reports.
Working cross-functionally to ensure product functionality, reliability, and successful deployment.