Interconnect Micro-Architect and Design Development Lead

Advanced Micro Devices, Inc•Austin, TX

About The Position

As a senior technical leader on AMD’s Infinity Fabric Architecture and RTL team, this role drives the development and execution of key IP within AMD’s scalable, coherent on-chip interconnect. The position works across component owners and engineering teams to turn architectural intent into high-quality implementations, resolve cross-component dependencies, and ensure designs meet functional, power, performance, area, and timing requirements. It partners with architecture, verification, physical design, integration, silicon, and program teams to shape development strategy, assess technical risk and implementation trade-offs, and drive complex IP from concept through silicon. The role combines deep RTL and microarchitecture expertise with broad technical leadership and influence across globally distributed teams supporting AMD CPUs, GPUs, and other advanced processor products. The successful candidate is an experienced, collaborative technical leader and self-starter who works effectively in a fast-paced, matrixed environment. They bring a strong background in microprocessor and ASIC development from concept to production, hands-on RTL expertise, sound engineering judgment, and a record of leading engineers through technical expertise and influence. Strong communication, analytical, and problem-solving skills are important for working with architects and cross-functional partners, resolving implementation challenges, evaluating trade-offs, and supporting timely decisions. The role is not eligible for visa sponsorship. This posting is for an existing vacancy.

Requirements

  • Strong industry experience in IP or ASIC design development, with substantial technical leadership across multiple components or engineering teams through silicon delivery.
  • Deep RTL design and implementation expertise in CPU, GPU, NoC, cache, or related processor subsystems.
  • Strong judgment on design quality, implementation constraints, and power, performance, area, and timing trade-offs.
  • Demonstrated ability to serve as an influential technical lead across globally distributed, matrixed teams, align component owners, resolve cross-team technical challenges, and drive execution collaboratively.
  • Ability to partner with architects, assess development scope and risk, guide complex design and silicon issue resolution, and communicate actionable recommendations to leadership.
  • Strong understanding of relevant processor and memory-system concepts, including coherency, ordering, and caches.
  • Strong written and verbal communication, analytical, and problem-solving skills.
  • BS, MS, or PhD degree in Electrical or Computer Engineering preferred.

Nice To Haves

  • BS, MS, or PhD degree in Electrical or Computer Engineering preferred.

Responsibilities

  • Drive development and execution across IP component owners and teams, align implementation priorities, resolve cross-component dependencies, and ensure component designs meet IP-level functional, power, performance, area, and timing requirements.
  • Partner with the IP architect to translate architectural intent into actionable development work, assess implementation feasibility, clarify requirements, and provide feedback on engineering trade-offs; bring architecture-impacting questions or changes to the architect for direction.
  • Lead top-down development scoping for new proposals and advise leadership on execution strategies across concurrent commitments using data-driven assessments of engineering effort, design reuse, dependencies, capacity, technical risks, and skills gaps.
  • Anticipate execution challenges and drive engineering responses to technical roadblocks, scope changes, and late-discovered bugs; use project-manager tracking information to assess technical progress, engage component owners, and support timely mitigation and priority decisions.
  • Drive implementation reviews, technical readiness assessments, and issue closure across component boundaries and with verification, physical design, integration, and silicon teams.
  • Reinforce design quality, clear technical ownership, and effective problem-solving throughout development.
  • Represent the team, or support leadership representation, in AMD design quality and time-to-market improvement initiatives.
  • Drive improvements to development processes, methodologies, tools, and team capabilities.
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