Integrated Circuit Layout Engineer

Great Sky•Boulder, CO

12d•$120,000 - $180,000•Hybrid

About The Position

Great Sky is a technology startup with a mission to rebuild AI from first principles, focusing on neuroscience-inspired hardware and algorithms. We are seeking a highly motivated integrated circuit layout engineer to optimize superconducting electronic circuitry for our AI hardware platform. While semiconductor IC layout experience is highly relevant, prior superconducting electronics experience is not required, as we will provide training on superconducting design rules, devices, and workflows. This role is open to mid-level through senior candidates, with the title and scope determined by experience. Today’s AI systems face limitations in data movement, latency, and energy efficiency. Great Sky is developing superconducting neural-network hardware that integrates ultra-fast analog computation, local memory, and optical fan-out. Scaling this platform necessitates disciplined IC layout, verification, and tapeout execution for increasingly complex superconducting circuits. You will play a key role in realizing highly efficient superconducting circuit layouts, contributing to the development of massively scaled neural networks capable of inference with significant speedups over current state-of-the-art systems.

Requirements

Bachelor’s degree in electrical engineering, computer engineering, physics, or a related field, or equivalent practical experience.
3+ years of experience in integrated circuit layout engineering in semiconductor or superconducting device domains.
Experience with IC layout tools and formats such as Cadence Virtuoso, KLayout, Calibre, GDSII/OASIS, PCells, DRC/LVS, or similar workflows.
Strong scripting ability in Python or a similar language, applied to parametric or automated layout generation.
Familiarity with post-layout extraction, parasitic-aware layout, or electromagnetic simulation workflows.
Direct contribution to at least one successful IC tapeout, preferably involving hierarchical layout, custom devices, or nonstandard process constraints.

Nice To Haves

Experience with development and customization of design rule check procedures for integrated circuit layouts.
Experience building or maintaining parametric cells, layout generators, or scripted layout flows.
Experience with numerical analysis of superconducting circuits.
Experience managing large tapeouts with complex foundry processes.

Responsibilities

Create layouts for individual superconducting device cells, reusable circuit blocks, and larger hierarchical structures such as neural-network circuits.
Optimize layouts for area, parasitics, device performance, manufacturability, and scaling.
Extension and improvement of our parametric/script-based layout engine to facilitate rapid scaling to even larger networks, using Python.
Support post-layout simulation and verification of passive and active superconducting circuits.
Collaboration with the fabrication team and external foundries to ensure successful manufacturing of chips.