Infra Systems Physical Architect

Qualcomm•San Diego, CA

18d•$140,000 - $210,000

About The Position

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives AI (Artificial Intelligence) on the Edge. Moreover, Qualcomm innovates in Automotive technology, Low Power High Performance Compute, communication, and high-end data processing to help create a smarter, greener connected future for all. In these latest high-end SoCs (System on Chip) designed by Qualcomm, Infra Systems Group provides the necessary and optimized solutions for connecting various best in class IPs like CPU, GPUs, NSPs, Modems and to the latest best in class DDR. As a Qualcomm ASIC Engineer, you will plan, define, model, design, optimize, verify, validate, Analyze, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path. Infra Systems team is actively seeking candidates for special Physical Architecture Engineering positions in our Infra Systems Architecture team. This team designs the best possible and optimized NoC (Network on Chip) which is highly floorplan driven. Also, as a Physical Architect engineer you will design architectures which can be implemented with best PPA. You will also produce custom methodologies best suited for implementing the NoC.

Requirements

Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.
PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
Deep knowledge on scripting and software languages including Python, PERL/TCL, Linux/Unix shell and C.

Nice To Haves

5+ years industry experience/coursework in the following areas:
NoC Implementation Experience
AMBA Protocol
Cache Coherency mechanisms
Constraining and Timing Analysis experience
Physical Aware Synthesis
Physical Aware DFT
Physical Design
Clock tree Planning
Spine
Mesh CTS
Custom Placement and Routing and Source Sync Clock Routing
Formal verification experience
Power domain analysis experience
Design Compiler/Fusion Compiler/Genus/Primetime/Prime power/Innovus a plus
TCL programming in above tool environments will really be handy

Responsibilities

Architecture, planning, and enablement of the best-in-class NoCs, customized implementation techniques, to achieve best in class latency, area, performance, and power goals.
Analysis, review, and improvement of functional and test (DFT) mode constraints for synthesis and place and route process.
Design recipes for physical aware synthesis, special placement strategies, optimal floorplanning, special clocking solutions (like mesh clock tree), power planning and analysis for lower power, optimized special routing techniques for reduced wire delays, timing optimization and closure with signal integrity for MMMC designs.
Analyze area, latency, timing, and power of the NoCs and estimate/plan physically aware NoC architectures for a more optimal one for the future.