IC Layout Engineer

SemiAnalysis•Hillsboro, OR

5d•Hybrid

About The Position

SemiAnalysis is an independent research and analysis firm specializing in the Semiconductor and AI industries. Our in-depth coverage spans the entire supply chain, from semiconductor fabrication processes to cutting-edge AI Models, software, and infrastructure. We are recognized as the leading authority on the semiconductor supply chain, with the highest concentration of industry experts within one team, and a deep-rooted passion for delving into the intricacies. We are a global team of analysts, each with extensive networks across the semiconductor supply chain and AI ecosystem, publishing industry shaping articles while participating in numerous conferences annually. Our newsletters reach more than 200,000 subscribers worldwide, including senior management and c-suite leaders at the leading semiconductor and AI companies. We also offer three core products: Industry Models – we develop and publish industry models on accelerator shipments, datacentre demand and supply, GPU total cost of ownership, and more. We work with hyperscalers, neoclouds, many of the world’s largest hedge funds, and government agencies. Core Research – our public equity markets product, geared towards financial investors, distils our deep technical research and knowledge into key insights on technology and product trends. Consulting and Technical Due Diligence – We conduct custom research and project work to guide key strategic and investment decisions for the largest private equity funds, leading venture capital firms, companies across the AI ecosystem, and government agencies. We are seeking an experienced IC Layout Engineer to join our team in Hillsboro, OR specializing in technical analysis of AI and datacenter hardware. This role involves analyzing the physical design, layout, and manufacturing implementation of leading-edge integrated circuits, and being an active contributor in the planning, tools, and processes required to acquire this information. You'll examine competing hardware at the layout level: reading floorplans, standard-cell fabrics, analog blocks, and physical implementation choices directly from the die, and translating that physical evidence into actionable architectural and competitive insights. This role requires a mix of technical expertise, design sensibility, and autonomy. You'll work independently and collaborate across our globally distributed team to examine and report on the design choices, optimizations, and trade-offs in competing hardware. The role rewards curiosity. The strongest people in this work are drawn to investigation: taking apart what they could have helped design, connecting physical evidence to architectural intent and roadmap signals, and following threads beyond any single prior role.

Requirements

We are hiring at all experience levels: 2+ years of industry experience in IC layout, physical design, place-and-route, custom/analog layout, or closely equivalent is preferred, but all exceptional candidates are encouraged to apply
Genuine exposure to leading-edge parts
Strong functional knowledge of digital and/or analog physical design flows (floorplanning, placement, CTS, routing, and signoff) on advanced process nodes
Working understanding of standard-cell architectures, cell utilization metrics, and area/power/performance optimization techniques
Strong functional knowledge of AI and datacenter hardware architecture (GPUs, CPUs, accelerators)
Direct experience in physical or electrical failure analysis, fault isolation, device debug, or related physical root-cause work, or strong aptitude to build it
Understanding of Design Technology Co-Optimization (DTCO) principles
Hands-on experience with, or strong aptitude for, semiconductor sample preparation and analytical tools such as precision polishing, FIB, SEM, and related electron-beam, X-ray, and compositional methods

Nice To Haves

Experience with industry P&R and custom layout tools (e.g., Innovus, Fusion Compiler, Virtuoso) and reading GDS/OASIS-level detail
Analog/mixed-signal layout expertise, including matching, shielding, guard rings, ESD, and high-speed interconnect layout
Product design or manufacturing R&D in advanced packaging (2.5D / 3D, high-speed interconnects, hybrid bonding)
Broad understanding of advanced manufacturing across CMOS logic, memory, and emerging technologies
Interpreting micrographs and electrical measurements to infer design and process characteristics, e.g., identifying cell libraries, track heights, fin/nanosheet configurations, and metal stack usage from imagery
Comfort developing plans for physical and electrical FA toolchains
Python for data analysis and engineering tasks (image analysis, layout metrics extraction, automation)
Strong professional network of experts
Statistical and process-control literacy

Responsibilities

Conduct detailed physical design and layout analysis of AI and datacenter hardware, including GPUs, ASICs, CPUs, custom accelerators, high-speed I/O, memory subsystems, and their packaging
Perform digital and analog floorplan analysis: identify functional blocks, partitioning strategy, hierarchy, power and clock distribution, and I/O placement from die-level imagery
Assess standard-cell library choices, cell utilization, placement density, and area/timing/power optimization strategies across designs and process nodes
Analyze analog/mixed-signal layout regions (SerDes, PLLs, PHYs, power management) and interpret matching, isolation, and routing choices
Drive end-to-end teardown and characterization; operate the analytical toolchain and direct more specialized work as needed
Identify competitive advantages, disadvantages, and generational changes in physical design, packaging, and system-level decisions
Apply Design Technology Co-Optimization (DTCO) and System Technology Co-Optimization (STCO) reasoning to interpret layout trade-offs and process-design interactions
Co-author technical research published by SemiAnalysis, combining physical observation, cross-industry context, and argument all in your words
Contribute to the growth and expansion of the lab's capabilities and output; bring your unique skills to a strong and expansive team