HPC System Architecture

Intel Corporation•Santa Clara, CA

6d•$220,920 - $311,890•Hybrid

About The Position

The HPC System Architect is the senior technical lead responsible for defining Intel's next-generation high-performance computing systems, owning forward-looking HPC system architecture from concept through committed definition. The role works directly with Intel CPU and GPU teams to shape silicon requirements and define system-level architectures for large-scale, scale-out production HPC clusters. It spans compute node design, memory and I/O balance, scale-out fabric and topology, and the software stack that determines application performance at scale. The architect engages with leading HPC customers—including DOE national laboratories, financial services institutions, oil and gas operators, and academic and government research computing centers—to translate workload and facility requirements into buildable system architectures and to translate Intel's roadmap into system concepts customers can commit to. The role also leads customer co-design and benchmark definition, evaluates emerging technologies, produces reference architectures and specifications, and provides technical direction and mentorship to the HPC architecture team. This position reports directly to Nic Dube, Corporate Vice President and General Manager of Data Center Systems and Solutions. It is eligible for Intel's hybrid work model, with time split between the assigned Intel site and off-site work. Primary locations are Santa Clara, California, and Hillsboro, Oregon. The role requires domestic and international travel for customer engagements and technical conferences.

Requirements

Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, Physics, or a related technical field.
At least 10 years of experience in HPC, data center, or server system architecture, design, or engineering.
At least 5 years of experience in a customer-facing or externally-facing technical role.
Demonstrated experience defining or deploying large-scale compute clusters.
Deep expertise in cluster-scale HPC system architecture, including CPU and GPU configuration, memory subsystem design, scale-out interconnect, and parallel storage.
Demonstrated experience defining systems around unreleased silicon and influencing CPU or accelerator requirements from a system and workload perspective.
Fluency with HPC workload characteristics and performance analysis, including quantitative reasoning about scaling behavior, communication patterns, and bottlenecks at scale.
Working knowledge of the HPC software stack, including MPI, OpenMP, GPU programming models, schedulers, and math and communication libraries.
Proven credibility with sophisticated technical customers in high-stakes procurement and co-design settings.
Strong understanding of the competitive HPC landscape, including alternative CPU and accelerator architectures, fabric options, and system vendor positioning.
Excellent written and oral communication skills, effective with both deep technical audiences and executive stakeholders.
Comfort with high ambiguity and a track record of driving clarity in undefined technical areas.
Willingness to travel domestically and internationally for customer engagements and technical conferences.
Consent to and pass an extended background investigation, subject to country law.

Nice To Haves

Master's degree or PhD in a relevant technical discipline.
Experience defining next-generation systems in partnership with CPU or GPU product and design teams.
Experience supporting DOE national laboratory or comparable large-scale public-sector HPC procurements.
Domain experience in a definitional HPC vertical, such as financial services, oil and gas and seismic processing, weather and climate, computational chemistry or biology, or manufacturing and CAE.
Hands-on experience with scale-out fabrics, including InfiniBand, Ultra Ethernet, or other high-performance interconnect.
Experience with system-level performance modeling and workload characterization at scale.
Experience with converged HPC and AI system design.

Responsibilities

Own system-level architecture for next-generation HPC clusters, including node definition, CPU and GPU configuration, memory bandwidth-to-capacity balance, I/O and parallel storage architecture, and scale-out fabric and topology.
Define scale-out interconnect architecture, including fabric selection, network topology, bisection bandwidth and blocking ratios, collective and communication performance, and resilience at thousands-of-node scale.
Partner with CPU and GPU teams to define product requirements for future HPC systems, using system-level and workload evidence to influence silicon definition while requirements remain open.
Build performance models projecting delivered application throughput at scale on unreleased silicon, and use them to drive configuration and roadmap decisions.
Lead architecture co-design and benchmark definition with leadership HPC customers, including acceptance criteria for standard and customer-proprietary application suites.
Drive HPC requirements into Intel's CPU, GPU, platform, and software roadmaps across DCG and product and design organizations.
Evaluate emerging technologies for next-generation HPC systems, including advanced memory, Ultra Ethernet and other scale-out fabric standards, optical interconnect, and heterogeneous accelerator integration.
Produce reference architectures and system specifications for platform teams, OEM and ODM partners, and system integrators.
Grow and lead HPC architecture capability within the team, providing technical direction and mentorship to architects and engineers.