High speed PHY System Architect

Intel•Hillsboro, CA

2d•Hybrid

About The Position

Responsibilities will include but are not limited to: Develop and drive analog and mixed-signal IP architectures, signal processing algorithms, and calibration algorithms for system-on-chip (SoC) independent AMS IPs. Conduct top-down architectural analysis of AMS systems and perform transistor-level feasibility studies for various AMS circuits. Design novel architectures and define microarchitectures for next-generation AMS IP to achieve optimal performance, power, and area for diverse product segments. Enhance system performance by leveraging digitally assisted analog techniques and optimizing the partitioning of analog and digital circuits. Evaluate trade-offs, explore innovative approaches, and provide proof-of-concept design alternatives for AMS systems. Collaborate with IP design and verification teams to define, develop, and validate robust AMS IPs for SoC integration. Support SoC architects, design engineers, and verification engineers in selecting, configuring, and validating SoCs that leverage AMS IPs. Perform modeling, simulation, and optimization for power, area, and performance metrics, analyzing test results to identify improvement opportunities. Define future AMS IP technology targets by influencing cross-functional roadmaps and reviewing emerging technology trends. The ideal candidate should show the following behavioral traits: Strong communication and collaboration skills, with the willing to mentor and technically guide team members.

Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or related STEM field with 9+ years of experience.
Master's degree in in Electrical Engineering, Computer Engineering, or related STEM field with 6+ years of experience.
PhD in Electrical Engineering, Computer Engineering, or related STEM field with 3+ years of experience.
Analog and mixed-signal circuit design within standard CMOS technologies, including op-amps, comparators, bandgap references, and linear regulators.
Backend verification tools such as Monte Carlo simulations, EMIR, and static/dynamic MOSFET voltage checks.
Analog behavior modeling and system-level understanding of AMS circuits.
Hands-on experience with transmission line theory and AMS system modeling.
Architectural feature definition, high-speed design techniques, and IP architecture definition.
Proven experience with high speed PHY designs from concept through qualification.

Nice To Haves

Proficiency in MATLAB or similar tool base modeling.
Experience in post-silicon debugging and high-volume productization of designs.
Familiarity with signal integrity and power integrity analysis.
Background in analog layout techniques, including floor-planning, matching, shielding, and parasitic optimization.

Responsibilities

Develop and drive analog and mixed-signal IP architectures, signal processing algorithms, and calibration algorithms for system-on-chip (SoC) independent AMS IPs.
Conduct top-down architectural analysis of AMS systems and perform transistor-level feasibility studies for various AMS circuits.
Design novel architectures and define microarchitectures for next-generation AMS IP to achieve optimal performance, power, and area for diverse product segments.
Enhance system performance by leveraging digitally assisted analog techniques and optimizing the partitioning of analog and digital circuits.
Evaluate trade-offs, explore innovative approaches, and provide proof-of-concept design alternatives for AMS systems.
Collaborate with IP design and verification teams to define, develop, and validate robust AMS IPs for SoC integration.
Support SoC architects, design engineers, and verification engineers in selecting, configuring, and validating SoCs that leverage AMS IPs.
Perform modeling, simulation, and optimization for power, area, and performance metrics, analyzing test results to identify improvement opportunities.
Define future AMS IP technology targets by influencing cross-functional roadmaps and reviewing emerging technology trends.