Head of Test Development Engineering

Ethernovia, Inc.•San Jose, CA

4d•$220,000 - $280,000•Hybrid

About The Position

The Head of Product Development Engineering will be responsible for taking Ethernovia’s products from NPI to HVM. This position requires a leader who is hands-on with semiconductor test development. You will bridge the gap between world-class networking chip designs and high-volume, automotive-grade silicon testing. The position is based in San Jose, CA.

Requirements

Bachelor's or Master's degree in Electrical Engineering or a related technical field
12+ years of experience in fabless semiconductor operations, specifically for complex, high-performance SOCs or networking ICs.
Expert in ATE 93K platform and Smartest, test method libraries and design of test hardware with robust SI/PI for wafer and final test.
Expertise with iJTAG, Scan (SSN), MBIST, Sensor, SerDes, LSIO/HSIO testing, security fusing and test automation for multi-site (x8, x16) parallel testing.
Expert in SLT testing using bare-metal, functional DVFS and benchmark testing and expert in multi-site handler automation framework and test log standards.
Experience with Analog characterizing high-speed communication chips on ATE and System to ensure all IO parameters are characterized and tested.
Experience defining DFT/DFM/DFD requirements for Ethernet PHY and Switch products and experience with scan and memory dump for debug.
Experience navigating the Automotive electronics ecosystem, including IATF 16949, ISO 26262, Safe launch and PPAP (Production Part Approval Process).
Understanding of high-bandwidth data-path products (Ethernet, Switching, or high-speed SerDes).
Expert level experience with ATE and SLT test hardware, test program development, high speed IO analog characterization and test automation.
Understanding of product life cycle from concept to end of life and leading pre-silicon review and readiness to enable seamless post-silicon bring-up

Nice To Haves

Experience with simulation, pattern generation, and pattern conversion.
Experience delivering high speed SerDes products to Tier-1 automotive OEMs.
Experience negotiating with and managing hardware vendors and OSATs.

Responsibilities

End to end, test architecture, infrastructure, hardware and methodology ownership from pre-silicon to post-silicon, working with Arch, Design, Desing verification, DFT, Security, SW/FW, System, Product and Q&R.
Own early engagement with Arch/DFT, System/SW and Security, on ATE and SLT test architecture and DFM / DFD to ensure debug ability and testability to spec.
Deliver manufacturing test programs from NPI bring-up to high volume manufacturing for high-speed Ethernet switch and PHY products ensuring signal integrity and power/performance standards are maintained at scale.
Own design of test boards ensuring SI/PI and test implementation across wafer test, final test and system level test, ensuring robustness and meeting test time.
Manage test labs, OSAT (test house), engagement with vendors for tester, prober, probe card, load board, system board, socket, handler, change kit and TCU.