Contract Hardware Engineer Mid- #26-18016

US Tech SolutionsSan Jose, CA

About The Position

We are seeking an experienced Hardware Engineer with 8-12 years of hands-on experience in analog IC design. The role involves architecting and designing high-performance analog/mixed-signal building blocks such as PLLs, ADCs/DACs, LDOs, Bandgaps, SerDes/PHY, and Op-Amps. The engineer will be responsible for translating and optimizing designs across different process geometries, including transitions from Planar to FinFET nodes. This position requires comprehensive simulation and verification, driving best practices in analog design methodology, and utilizing automated design tools and script-based verification.

Requirements

  • 8–12 years of hands-on experience in analog IC design.
  • Experience with Cadence Virtuoso (ADE/Maestro) for custom design/schematic.
  • Experience with simulation tools like Spectre, ClientICE, or CustomSim.
  • Experience with physical verification tools like Mentor Calibre (DRC/LVS/PEX) or Synopsys IC Validator.
  • Experience with reliability/sign-off tools like Voltus, RedHawk, or similar power/IR integrity tools.
  • Experience with multi-node design and optimization across different process geometries.
  • Proficiency in performing comprehensive pre-layout and post-layout simulations.
  • Familiarity with script-based verification using Python/SKILL/Tcl.

Responsibilities

  • Architect and design high-performance analog/mixed-signal building blocks (e.g., PLLs, ADCs/DACs, LDOs, Bandgaps, SerDes/PHY, Op-Amps).
  • Translate and optimize designs across different process geometries, including transition strategies from Planar (e.g., 28nm) to FinFET (e.g., 16nm, 7nm...) nodes.
  • Perform comprehensive pre-layout and post-layout simulations, including Monte Carlo, corner analysis, noise analysis, and reliability modeling (EM/IR/Aging/BTI/HCI).
  • Drive best practices in analog design methodology, including the adoption of automated design tools and script-based verification (Python/SKILL/Tcl).
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