Hardware Engineer, Architect

Normal Computing Corporation • Palo Alto, CA

1d

About The Position

Normal Computing builds silicon that turns thermal noise from an obstacle into a computational resource. Conventional chips spend most of their energy forcing determinism onto physics; ours compute with it. Stochastic, in-memory, asynchronous: the result is 10-100× more AI inference per dollar, per watt. We co-design the full stack: AI-native EDA systems in production with the world's largest semiconductor companies, and the advanced ASICs they make possible. Backed by $85M+ from the world's leading deep-tech investors and built by scientists, engineers, and operators from the labs that built modern computing. Normal works as one team across New York, Silicon Valley, London, Copenhagen, and Seoul. We hire people who want the hardest version of their craft, across every discipline, at every seniority.

The Role
As a Hardware Engineer, Architect, you will define the silicon and system microarchitecture for our custom unconventional compute platform—driving the architectural trade-offs that unlock a 100–1000x leap in energy efficiency over traditional digital chips for LLM and diffusion model inference.
You will lead the hardware/software co-design efforts to break the von Neumann memory wall. By translating transformer architectures (KV-cache management, attention mechanisms) and diffusion execution flows into custom mixed-signal compute tiles, memory hierarchies, and tile interconnects, you will set the blueprint for our hardware. Working closely with compiler, RTL, and analog teams, you will build performance models, establish microarchitectural specifications, and ensure our custom silicon delivers maximum throughput-per-watt on real-world generative AI workloads.

Requirements

• A degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent work experience.
• Substantial experience in architecture or microarchitecture of high-performance digital systems: AI accelerators, compute engines, or similarly complex logic.
• Fluency moving between algorithm-level analysis and hardware specification.
• Experience with simulation-driven architecture.
• Familiarity with quantization and reduced-precision approaches for inference and their implementation implications.
• Experience writing microarchitecture specifications and working closely with RTL engineers through implementation.
• Proficiency in Python or C++ for performance modeling and analysis, and familiarity with SystemVerilog or equivalent RTL.
• Comfort operating in an environment where the architecture is actively being discovered alongside the work.

Nice To Haves

• PhD welcome but not required; the bar is the work, not the credential.
• You have shaped and directed the structures inside a chip, not just consumed them from the outside.
• You can read a profile of a workload and translate it into datapath widths, pipeline stages, and area/power estimates without losing the thread on either side.
• You know which questions each tool can answer and which it cannot.
• You understand the cost of a bit at the hardware level, not just the model level.
• You do not need the answer to be already known to make progress on it.

Responsibilities

• Define the architecture and microarchitecture of novel AI accelerator compute blocks: PE array design, datapath organization, and support for efficiency techniques such as sparsity exploitation and reduced-precision computation.
• Translate workload analysis and research findings into hardware specifications.
• Identify where architectural innovation creates the most leverage, define the structures that realize it, and produce microarchitecture documents unambiguous enough for RTL engineers to implement against.
• Reason across the full stack and defend PPA tradeoffs at every level.
• Move between algorithm-level workload behavior, memory hierarchy, on-chip interconnect, and physical design constraints.
• Make the call when the data is incomplete, and articulate why under scrutiny from our Systems Architect and the research team.
• Partner with the compiler lead on ISA co-design.
• Direct block-level pre-silicon validation.
• Decide which microarchitecture questions need to be answered, and the appropriate platform.
• Partner with our FPGA Design Engineers, who own implementation and bring-up, to de-risk decisions before tapeout.
• Work with the Systems Architect to make sure there are no gaps from block to System-level validation.
• Stay current with the AI accelerator research landscape and be able to articulate clearly where Normal's approach differs from existing solutions and why that matters.
• Read, possibly publish, and not just consume research.

Benefits

• We celebrate diversity and are committed to creating an inclusive environment for all employees.
• All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other legally protected status.
• Normal Computing is committed to providing reasonable accommodations to individuals with disabilities.
• Normal Computing may collect, use, and store your personal information for employment-related purposes in accordance with our Privacy Policy.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Education Level: Associate degree