Hardware Design Engineer Technical Lead
About The Position
The Hardware Design Technical Lead is a key member of the Cisco Purpose Built Switch hardware team. This role involves defining and designing the next generation Hyperscaler Switch hardware based on Silicon One and/or merchant ASIC. The individual will be responsible for system and board level specification, schematic capture, FPGA design, ASIC/System level bring up and troubleshooting. They are expected to bring up the system to work with multiple groups including ASIC, DFT, Signal Integrity, software, Diagnostics and Manufacturing team to resolve any design issues. This role also includes debugging and troubleshooting in labs using scopes and analyzers, and acting as a technical liaison with major component Suppliers for the product.
Requirements
- Bachelor's degree in Electrical Engineering or Computer Engineering or Telecommunications and 8+ years of experience, or Master’s degree in Electrical Engineering or Computer Engineering or Telecommunications and 6+ years of experience, or PhD in Electrical Engineering or Computer Engineering + 3 years in system level development.
- Prior experience with common HW technology, including power, clock, memory, CPU, and variety of system interfaces.
- Previous experience with complex high-speed board design and board bring-up.
- Prior experience with schematics/layout, Hardware bring-up, trouble-shooting, system level testing.
- Experience with working with Software team on system bring-up and porting, devices configuration (registers level).
Nice To Haves
- Experience with schematics, PCB and Verilog HDL/VHDL design
- Experience on the scripts (Python, Tcl, etc.)
- Experience with lab bring up and design validation of products
- Knowledge on the Ethernet protocol is a plus
- Experience with access switch Ethernet interfaces: gigabit, multi gigabit, 10 gigabit.
- Experience with high speed Ethernet interfaces: 25G, 100G, 400G, 800G.
- Experience with DRAM, CPU subcomplex and control interfaces such as PCIe, I2C, SPI, MDC/MDIO
- Self-motivation, teamwork and strong communication skills are essential.
Responsibilities
- Define and design the next generation Hyperscaler Switch hardware based on Silicon One and/or merchant ASIC.
- Responsible for system and board level specification, schematic capture, FPGA design, ASIC/System level bring up and troubleshooting.
- Bring up the system to work with multiple groups including ASIC, DFT, Signal Integrity, software, Diagnostics and Manufacturing team to resolve any design issues.
- Debug and troubleshoot in labs using scopes and analyzers.
- Act as technical liaison with major component Suppliers for the product.
Benefits
- medical, dental and vision insurance
- a 401(k) plan with a Cisco matching contribution
- paid parental leave
- short and long-term disability coverage
- basic life insurance
- Cisco restricted stock units
- 10 paid holidays per full calendar year
- 1 floating holiday for non-exempt employees
- 1 paid day off for employee’s birthday
- paid year-end holiday shutdown
- 4 paid days off for personal wellness
- 16 days of paid vacation time per full calendar year (non-exempt employees)
- flexible vacation time off program (exempt employees)
- 80 hours of sick time off provided on hire date and each January 1st thereafter
- up to 80 hours of unused sick time carried forward
- Additional paid time away may be requested to deal with critical or emergency issues for family members
- Optional 10 paid days per full calendar year to volunteer
- annual bonuses (for non-sales roles)
- performance-based incentive pay (for sales roles)
Stand Out From the Crowd
Upload your resume and get instant feedback on how well it matches this job.
What This Job Offers
Job Type
Full-time
Career Level
Senior
