GPU Physical Design Engineer

Apple • Austin, TX

3d • Onsite

About The Position

Work closely with the FE team to understand chip architecture and drive physical aspects early in design cycle. Drive best in class PD construction and optimization recipes for performance, power and Area (PPA). Work on cutting edge designs in the latest technological nodes. Drive methodologies and "best known methods" to streamline PD work, coming up with guidelines and checklists, driving execution, and supervising progress. Drive work among place and route engineers, set goals and breakthroughs, plan short and long-term work, understand dependencies between different domains like top, STA, block place and route. Lead and resolve design and flow issues related to physical design, identify potential solutions and drive execution.

Requirements

• Utilizing industry standard automated place and route tools such as Cadence-Innovus to perform place and route of GPU partitions.
• Working with FE teams to provide IP feedback to improve design for metrics such as timing and congestion.
• Utilizing design knowledge and innovative physical construction methodologies to improve power performance and area of GPU designs.
• Utilizing knowledge of multi voltage and power gated designs to handle low power design requirements.
• Utilizing hierarchical design approach to handle multiple instantiated designs in PNR and understand their unique challenges related to budgeting and floor planning.
• Integrating IP from both internal and external vendors and being able to specify and drive IP requirements in the physical domain.
• Working on various process related design issues in lower tech nodes including Design for Yield and manufacturability.
• Designing large GPU designs (>20M gates) with frequencies in excess of 1GHz.
• Utilizing scripting languages such as TCL or Python to help automate physical design tasks and develop utilities to help with querying design for metrics.
• Optimizing low power design techniques such as clock gating, custom clock construction, power gating, and multi-voltage technique threshold strategies.

Responsibilities

• Work closely with the FE team to understand chip architecture and drive physical aspects early in design cycle.
• Drive best in class PD construction and optimization recipes for performance, power and Area (PPA).
• Work on cutting edge designs in the latest technological nodes.
• Drive methodologies and "best known methods" to streamline PD work, coming up with guidelines and checklists, driving execution, and supervising progress.
• Drive work among place and route engineers, set goals and breakthroughs, plan short and long-term work, understand dependencies between different domains like top, STA, block place and route.
• Lead and resolve design and flow issues related to physical design, identify potential solutions and drive execution.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior