Fullchip Floorplan Design Engineer

Intel • Austin, TX

15h • Hybrid

About The Position

The world is transforming - and so is Intel. Intel is a company of bold and curious inventors and problem solvers who create some of the most astounding technology advancements and experiences in the world. With a legacy of relentless innovation and a commitment to bring smart, connected devices to every person on Earth, our diverse and brilliant teams are continually searching for tomorrow's technology and revel in the challenge that changing the world for the better brings. We work every single day to design and manufacture silicon products that empower people's digital lives. Come join us and do something wonderful. The Role: We are looking for a talented and motivated Physical Design Floorplanning Engineer to join our team. In this role key responsibilities are: Top-down SoC Floorplan activities like best IP placement for latency/area in collaboration with architects, partitioning, PG grid creation, pin-cutting, bump-planning by working with package/platform. Estimate die-area and define optimal physical dimensions for SoC by including product costs like die-per-reticle, right technology selection/metal stack and reuse from different product family. Drive execution, and supervise progress of smaller blocks or sub-systems influencing their physical placement, shape, and channel planning to help them achieve best area and convergence schedule. Plan short and long-term work schedule, understanding dependencies between different domains like top, block place and route. Responsibilities: Collaborate with other stake holders like the clock design to deliver the physical block level floorplans for APR and with the power delivery team on tradeoffs for metal allocation for signal and power. Experienced in industry standard tools. Help drive methodologies, tools and best known methods to streamline Floorplan Physical Design work to achieve best-in-class on schedule delivery. Intel is in the process of securing office space in Fort Collins, Colorado. Once the site is operational, this will be an addition site.

Requirements

• Bachelor in Electrical/Electronics/Computer Engineering with 4+ years of relevant experience or Master's degree in Electrical/Electronics/Computer Engineering with 3+ years of relevant experience.
• 3+ years of experience using industry-standard EDA tools for floorplanning and APR.
• 1+ years of experience with Synopsys Fusion Compiler.
• 4+ years of experience with TCL, Python or Perl programming.
• 2+ years of experience with Calibre or ICV verification.

Nice To Haves

• Good Knowledge with all aspects of ASIC integration including Floorplanning, Clock and Power distribution, Global signal planning, I/O planning and Macro placement.
• Familiar with hierarchical design approach, top-down design, handling MIB (multiple instantiation blocks), routing and physical convergence.
• Deep knowledge of SoC Floorplan requirements like multiple voltage and clock domains, Level Shifters, thermal management, Die-to-Die interconnects, and package interactions.
• Expertise with Floorplanning tools - ICC2/FC, Place and Rout flows, and Physical Design Verification Flows is required.
• Experience with large subsystem designs (20M gates) with frequencies in excess of 2GHz.
• Good automation skills/focus with coding familiarity in tcl/perl/python
• Excellent communication and teamwork skills

Responsibilities

• Top-down SoC Floorplan activities like best IP placement for latency/area in collaboration with architects, partitioning, PG grid creation, pin-cutting, bump-planning by working with package/platform.
• Estimate die-area and define optimal physical dimensions for SoC by including product costs like die-per-reticle, right technology selection/metal stack and reuse from different product family.
• Drive execution, and supervise progress of smaller blocks or sub-systems influencing their physical placement, shape, and channel planning to help them achieve best area and convergence schedule.
• Plan short and long-term work schedule, understanding dependencies between different domains like top, block place and route.
• Collaborate with other stake holders like the clock design to deliver the physical block level floorplans for APR and with the power delivery team on tradeoffs for metal allocation for signal and power.
• Help drive methodologies, tools and best known methods to streamline Floorplan Physical Design work to achieve best-in-class on schedule delivery.

Benefits

• We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.
• Find out more about the benefits of working at Intel .

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Number of Employees: 5,001-10,000 employees