Fullchip Floorplan Design Engineer

Advanced Micro Devices, Inc • Markham, ON

6h • Hybrid

About The Position

As part of AMD’s S3 (Semi-Custom) organization, you will work within the Physical Design integration team to translate SoC RTL into a full-chip floorplan, enabling downstream implementation and first-pass silicon success. This role operates at the intersection of architecture, RTL, DFT/DFX, and physical design, with a primary focus on defining chip-level structure early in the design cycle. It is a highly hands-on, execution-driven role requiring deep expertise in full-chip floorplanning and physical design.

Requirements

• Hands-on physical design engineer with strong experience in full-chip floorplanning and SoC implementation
• Comfortable working across teams, driving early-stage implementation decisions, and translating design intent into practical physical structures
• Strong ownership, problem-solving ability, and consistently deliver high-quality results in fast-paced, technically complex environments

Nice To Haves

• Experience in SoC physical design with successful tapeouts
• Strong ownership of full-chip floorplanning (partitioning, macro placement, integration)
• Solid understanding of physical design flows and impact on timing, power, and implementation
• Hands-on experience with Fusion Compiler or similar tools (e.g., Innovus)
• Experience with feedthrough planning, bus topology, and timing-aware floorplanning
• Understanding of SoC architecture (e.g., AXI, source-synchronous interfaces, test)
• Proven collaboration with RTL, IP, DFT/DFX teams
• Scripting skills (Tcl, Perl, Python, or Shell) for automation
• Experience with large-scale SoC designs and low-power considerations
• Experience improving design productivity through automation or advanced methods

Responsibilities

• Own full-chip floorplanning (partitioning, macro placement, integration)
• Translate RTL → full-chip floorplan (chip structure, block definition)
• Plan pins, feedthroughs, and bus topology (incl. source-synchronous interfaces)
• Define repeater strategy for timing and signal integrity
• Optimize floorplan for timing, power, and area (PPA)
• Run feasibility / tradeoff analysis for floorplanning decisions
• Collaborate with RTL, architecture, DFT/DFX, and PD teams
• Use tools like Fusion Compiler / Innovus for implementation
• Build automation (Tcl / Perl / Python) to improve execution

Benefits

• AMD benefits at a glance

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Education Level: Associate degree