Full Chip Power Integrity Engineer

Altera • San Jose, CA

1d

About The Position

About Altera
Altera is a leading supplier of programmable logic solutions that enable customers to innovate faster and deliver differentiated products across cloud, communications, industrial, automotive, aerospace & defense, and edge applications. Our FPGAs power the world’s data infrastructure and intelligent systems, delivering high performance, flexibility, and scalability.

At Altera, you’ll join a team of passionate engineers solving complex technical challenges in advanced silicon technologies. We foster a collaborative culture that values innovation, technical excellence, and continuous learning.

About the Role
As a Senior Full Chip Power Integrity Engineer, you will be a key member of the Full Chip Integration Reliability Team, responsible for all aspects of FPGA power intent and reliability across complex SoC and FPGA architectures. In this role, you will drive power intent verification using UPF, perform power electrical rule checking, and conduct power-up and power-down SPICE simulations at both block and full system levels. You will also lead system-level power delivery network (PDN) analysis to ensure robust and reliable silicon operation across process, voltage, and temperature corners.

This position requires strong cross-functional collaboration with design, verification, physical design, package, and reliability teams to verify, debug, and sign off on system-level reliability requirements. You will play a critical role in ensuring power architecture correctness, integrity, and long-term reliability for next-generation FPGA products.

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field
• 8+ years of experience in power integrity, power intent, or reliability engineering for advanced ASIC/SoC/FPGA designs
• Proven experience as part of a Full Chip Integration or Reliability team responsible for FPGA power intent and reliability
• Strong hands-on experience with UPF-based power intent definition and verification
• Experience performing power electrical rule checking and debugging power intent violations
• Experience conducting power-up and power-down SPICE simulations at block and system levels
• Experience with system-level power delivery network (PDN) analysis and reliability signoff
• Strong understanding of EM/IR, voltage droop, and power integrity fundamentals
• Demonstrated ability to work cross-functionally to verify, debug, and sign off system-level reliability items

Nice To Haves

• Master’s degree or PhD in Electrical Engineering or related discipline
• Familiarity with FPGA architectures and programmable logic design
• Experience with industry-standard EDA tools for power analysis and reliability signoff
• Knowledge of package and board-level power delivery interactions
• Experience supporting silicon bring-up and failure analysis

Responsibilities

• Define, implement, and verify FPGA power intent using UPF across full-chip and subsystem designs
• Perform power-aware verification and power electrical rule checking to ensure architectural correctness
• Conduct power-up and power-down SPICE simulations at block and system levels
• Lead full-chip and system-level power delivery network (PDN) analysis and validation
• Analyze IR drop, EM, voltage droop, and dynamic power integrity scenarios
• Collaborate with RTL, DV, physical design, package, and reliability teams to debug and resolve power integrity issues
• Develop methodologies and flows to improve power reliability signoff
• Drive system-level reliability closure across PVT conditions
• Support silicon bring-up and post-silicon power integrity validation as needed

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level