Principal Engineer, Signal-Integrity and Power-Integrity

SK hynix America•San Jose, CA

11d•$185,000 - $220,000•Onsite

About The Position

SK hynix America is seeking a Principal Engineer to lead the Signal‑Integrity and Power‑Integrity (SIPI) strategy for next‑generation advanced packaging technologies. In this role, you will lead the design, analysis, and validation of next generation advanced packaging solutions for HBM and beyond HBM such as logic-memory integration. The position requires deep technical expertise in high-speed interface design, collaboration with global R&D teams, and contributions to industry standards for advanced packaging.

Requirements

Education: Ph.D. in Electrical Engineering, or a related field (or Master’s degree with 5+ years of relevant industry experience).
Experience: ≥ 5 years of hands‑on SIPI engineering in advanced semiconductor packaging.
Technical Expertise: Deep knowledge of 2.5 D/3 D package architectures, HBM, interposer, TSV, high‑speed I/O standards, and power‑delivery networks. Proven proficiency with SIPI simulation tools (e.g., Ansys SIwave/RedHawk, Cadence Sigrity).
Design Flow Mastery: Strong background in electromagnetic extraction, multi‑port S‑parameter analysis, power‑network optimization, and tape‑out sign‑off processes for complex packages.
Leadership Skills: Demonstrated ability to influence multi‑disciplinary teams, drive technical decisions, and mentor senior engineers.
Communication: Excellent verbal and written communication skills; ability to present complex technical concepts to both engineering and executive audiences.

Nice To Haves

Hands-on experience with 2.5D/3D packaging for HBM, interposers, or GPU-memory integration.
Expertise in power integrity (PI) for 3D-stacked memory systems, including PDN impedance profiling and IBIS model validation for HBM.
In‑depth familiarity with industry standards such as PCIe Gen5/Gen6, CXL, UCIe, and JEDEC memory specifications.
Familiarity with advanced packaging workflows from ball map definition to tape-out for interposer-based designs.
Proficiency in scripting/automation (Python, TCL, SKILL) to create custom analysis flows and improve productivity.
Experience validating high-speed memory interfaces using oscilloscopes, VNAs, and compliance test platforms specific to 3D packaging.
History of published technical papers, patents, or conference presentations in advanced packaging or SIPI.

Responsibilities

Strategic Leadership: Define and own the SIPI roadmap for advanced PKG families, aligning technical direction with product and business goals.
Architecture & Design: Lead the creation of high‑performance SiP architectures (HBM, interposer, 3 D stacks) and validate power‑delivery and signal‑integrity across the full stack—from silicon to substrate.
Methodology Development: Invent and propagate best‑practice SIPI methodologies, including electromagnetic extraction, multi‑port S‑parameter modeling, and power‑network analysis for complex packaging environments.
Technical Ownership: Oversee the end‑to‑end design flow (package definition, simulation, layout sign‑off, tape‑out) and drive continuous improvement of tools, scripts, and automation.
Mentorship & Talent Development: Coach senior and junior engineers, fostering expertise in SIPI analysis, tool usage, and design verification; champion knowledge‑sharing across global teams.
Risk Management & Sign‑off: Conduct comprehensive risk assessments, lead design reviews, and deliver final SIPI sign‑off packages that meet performance, reliability, and schedule targets.