Enablement Engineer, On-chip power delivery, Sr

Qualcomm • San Diego, CA

5d

About The Position

Qualcomm has a position in San Diego, CA, focusing on on-chip power grid optimization for sub 2nm nodes. The role involves driving 3D system integration, balancing performance and cost, and includes responsibilities such as integrated VRs and backside power delivery. Ideal candidates should have a background in 2.5D/3D on-chip integration, process technology, and design enablement. Qualcomm is the world leader in wireless chipsets powering the majority of 4G and 5G devices, the largest fabless semiconductor in the world, and is widely regarded as one of the most employee friendly companies in the high-tech marketplace. Qualcomm central hardware system (CHS) team has a broad array of responsibilities that include developing cutting edge package technology, developing system-level power and signal integrity from transistor to PMIC on a wide range of products used by millions customers.

Requirements

• Understanding of Electronics, Circuitry, and Semiconductor Physics/Devices for PDN structure design and IR results analysis
• Programming skills, such as Python, Matlab for automation, data analysis, and results summary
• Knowledge of digital design PnR from floorplan stage and IP placement
• Knowledge of digital design PnR flow
• Being familiar with SPICE
• Good communication skills
• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
• Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
• PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

Responsibilities

• Develop power grid structure for key IPs (CPU, GPU, SoC, etc.) and check IR/EM (Electron-Migration) performance
• Provide design solutions for IR/EM and routing optimization
• Work with process team for process tuning to achieve better PDN (Power Delivery Network) design
• Support advanced process node PDN sign-off checks, including PDN quality check, static/dynamic IR sign-off, and EM sign-off for successful chip tape-out
• Provide guidance to PnR (Place and Route) designer on PDN issue fixing
• Drive backside power delivery solution balancing performance and cost

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level