Front-End Design Engineer

Qualcomm•San Diego, CA

3d•$115,600 - $173,400

About The Position

In this position, you will be responsible for RTL design and verification of digital IPs used across the board in Qualcomm chips. You will have the opportunity to work on critical high-speed clock IPs, power-sequencing blocks integral to Qualcomm’s low power designs, custom FIFOs and high-speed latch arrays. The position also involves close collaboration with SOC design and verification teams on specification, integration, development, and support of front-end deliverables for these Soft/Hard-Macros.

Requirements

Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
OR Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
OR PhD in Science, Engineering, or related field.
Bachelors – Electrical Engineering, Bachelors - Science
2+ years ASIC design, verification, or related work experience
Strong knowledge in digital logic design (Data path and Finite Sate Machine (FSM) Design)
Verilog
System Verilog
Perl
Circuit Design

Nice To Haves

Master’s degree in science, Engineering or related field
2+ years of professional or academic experience with RTL design or verification of digital IPs
Design verification knowledge and experience with design testbench suites.
Good understanding of OOP concepts. Experience in HVL such as System Verilog, UVM/OVM & System C
Familiarity with Power-aware Verification is a plus
Good working knowledge of synthesis and STA
Knowledge of low power design techniques
Ability to work with transistor-level circuit designers
Familiarity with ASIC backend integration tools for PNR is a plus
Familiarity with IP delivery collaterals including behavior model, upf libs, LEF view, etc is a plus
Automation knowledge (python) etc. will be a significant plus

Responsibilities

RTL design and verification of digital IPs
Work on critical high-speed clock IPs, power-sequencing blocks, custom FIFOs and high-speed latch arrays
Close collaboration with SOC design and verification teams on specification, integration, development, and support of front-end deliverables for Soft/Hard-Macros
Execute test plans, write checkers, assertions and develop stimulus using simulation and formal verification methodologies