In this role you will use SystemVerilog and UVM methodologies, working from specifications to deliver coverage-closed, verified, and debugged FPGA designs. You will be responsible for developing verification environments and leveraging 3rd party VIP as appropriate. You will verify FPGA-based designs, blocks, and sub-systems within complex systems, working closely with design teams. You will be part of a strong and experienced engineering team, contributing to high-performance FPGA development projects.
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Job Type
Full-time
Career Level
Senior
Education Level
No Education Listed