FPGA System Architect

Associated Universities • CHARLOTTESVILLE, VA

2d • Onsite

About The Position

The National Radio Astronomy Observatory (NRAO), managed by Associated Universities, Inc. (AUI), is a leading research and development organization in radio astronomy. The Central Development Laboratory (CDL) at NRAO is seeking an experienced FPGA System Architect to join its digital design team. This role involves leading the technical execution, integration, and deployment of a digital signal processing system for a next-generation radio telescope synthesis array. The engineer will guide the system through implementation, design reviews, integration, and operational deployment, while also supporting requirements refinement. CDL's digital design team develops advanced digital signal processing systems crucial for radio astronomy research. The selected candidate will lead the technical development and execution of FPGA-based systems, focusing on high-throughput digital signal processing, including digitized receiver data acquisition, calibration processing, and frequency channelization. This position combines system-level technical ownership with hands-on FPGA development, including RTL development and system integration. The role requires strong time management, the ability to manage multiple concurrent efforts, effective cross-disciplinary communication, and the ability to balance system-level ownership with hands-on development. The position is based at the Central Development Laboratory in Charlottesville, Virginia.

Requirements

• Bachelor's degree in Electrical Engineering or related field
• Eight years of experience developing complex FPGA-based digital signal processing systems
• Experience leading the architecture, development, integration, and deployment of FPGA-based systems
• Experience defining system architectures, subsystem interfaces, and data flows across FPGA processing, embedded software, and external system interfaces
• Experience with high-throughput DSP systems, including digitized signal acquisition, calibration processing, and channelization
• Experience leading technical teams, coordinating multi-disciplinary efforts, and leading subsystem design reviews
• Experience with timing and synchronization concepts for high-throughput FPGA systems
• Solid understanding of digital design fundamentals and FPGA development flows, including synthesis, timing analysis, place-and-route, and system integration
• Hands-on experience with RTL development using hardware description languages
• Experience with high-speed interfaces and data transport technologies relevant to FPGA systems
• Observatory employees must be authorized to work in the United States.
• The Observatory presently cannot sponsor H-1B Visas for this position.

Nice To Haves

• Experience defining and executing FPGA verification and validation approaches, including simulation, system integration, and end-to-end testing
• Experience with RF-series FPGA devices with integrated ADC capability or similar direct digitization platforms
• Experience with radio astronomy, software-defined radio, or high-performance signal processing systems
• Experience with receiver calibration techniques and frequency channelization implementations
• Familiarity with version control tools and collaborative development workflows
• Experience with Linux-based embedded environments and hardware/software integration
• Familiarity with mechanical, thermal, and SWaP (size, weight, and power) considerations for FPGA-based systems and deployment environments

Responsibilities

• Lead the architecture, design, integration, and deployment of the antenna-side FPGA-based digital signal processing system from ADC input through channelized output
• Lead work package planning, technical scheduling, and execution tracking
• Define subsystem decomposition, interfaces, and data flow across FPGA processing elements, embedded software, timing and synchronization systems, digitizers, and external data transport systems
• Execute subsystem development against system requirements and support requirements refinement and change requests during system development
• Define and evaluate implementation tradeoffs involving FPGA resource utilization, latency, throughput, timing margins, and implementation complexity
• Define and guide implementation of FPGA-based processing functions, including receiver calibration and frequency channelization
• Contribute to FPGA implementation activities including RTL development, verification, timing analysis, and system integration, as required
• Lead subsystem design reviews and contribute to system-level design reviews
• Coordinate technical activities across FPGA, embedded software, and related engineering efforts within the work package
• Provide technical direction and task coordination for engineering staff and external collaborators
• Document system architectures, interfaces, design decisions, and verification approaches clearly

Benefits

• Excellent paid time off (13 holidays, annual accrual of up to 24 vacation days)
• Medical, dental and vision plans are effective on the first day of employment.
• AUI’s retirement benefit contributes an amount equal to 10 percent of a qualified participant’s base pay with no required employee contribution.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior