FPGA Software

Cowboy Space Corp.•San Carlos, CA

1d•$150,000 - $200,000

About The Position

Cowboy Space Corp. is building the infrastructure to power and connect the orbital economy. Our satellites operate in Low Earth Orbit to collect sunlight and enable a new class of capabilities—from powering on-orbit compute, to transmitting energy via infrared lasers (space-to-earth and space-to-space), powering on-orbit compute to delivering secure, high-bandwidth optical data. By rethinking how energy and data are generated and distributed in space, we’re unlocking entirely new ways to operate both in orbit and on Earth. Founded in 2024 by Baiju Bhatt (co-founder of Robinhood), Cowboy Space Corp. is backed by leading investors and built by a team from top aerospace and defense organizations. We’re moving quickly to solve complex technical challenges and build a new category of space infrastructure. About the Role We're looking for an experienced FPGA/RTL engineer to help build the digital backbone of our compute payload — the hard-real-time logic that connects high-speed image sensors to embedded compute. You'll design and own RTL for sensor interfacing, high-throughput pixel capture into DDR via DMA, and memory-mapped register interfaces to embedded Linux running on ARM-based SoCs. This is active development on a live flight program with near-term launch milestones: you'll join a small, senior team, take full ownership of workstreams from day one, and see your designs fly. The Role This role sits at the boundary between hardware and software. You will work across platform firmware, FPGA logic, board bring-up, system management, and autonomous recovery systems to ensure reliable operation from first power-on through orbital deployment.

Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field
5+ years of experience in FPGA/RTL design, including architecture, RTL coding, verification, synthesis, and timing closure
Proficiency in SystemVerilog or Verilog for production FPGA development
Hands-on experience with FPGA + ARM SoC platforms (e.g., Xilinx/AMD Zynq or Zynq UltraScale+) and AMD/Xilinx toolchains (Vivado, Vitis, Petalinux)
Experience designing high-speed digital interfaces and DDR/DMA-based datapaths
Experience integrating FPGA logic with embedded software, including memory-mapped register interfaces and driver-level debugging
Hands-on hardware bring-up and lab debugging experience with oscilloscopes, logic analyzers, and embedded debug tools
Demonstrated ability to own open-ended design problems independently and carry them from hardware
Hands-on experience in embedded systems, platform firmware, BMC development, or hardware bring-up engineering.
Strong proficiency in C/C++ and Python.
Deep understanding of platform initialization and boot architectures.
Strong familiarity with hardware communication interfaces including I2C, SPI, UART, GPIO, and JTAG.
Experience debugging hardware/software interactions at board and system level.
Familiarity with FPGA or CPLD development workflows using Xilinx or Altera platforms.
Strong systems-level debugging and problem-solving skills.

Nice To Haves

Master's degree in Electrical Engineering, Computer Engineering, or a related discipline
Experience in aerospace, defense, semiconductor, or other high-reliability development e
Experience with image sensor interfaces and camera pipelines (e.g., MIPI CSI-2, LVDS/SLVS, SubLVDS) or other high-bandwidth sensor front-ends
Familiarity with Versal ACAP architecture and/or Intel/Altera devices (Cyclone 10) and Quartus toolflows
Experience with simulation and verification tools such as Questa/ModelSim, Xcelium, or Verilator, and with UVM or other structured verification methodologies
Working knowledge of embedded Linux internals — device trees, kernel drivers, userspace/hardware interaction — on ARM platforms
Proficiency with C/C++, Python, and TCL for bring-up, test automation, and tooling
Experience with hardware-in-the-loop testing and automated regression of FPGA designs
Familiarity with fault-tolerant design and radiation effects mitigation (SEU scrubbing, TMR, configuration memory integrity) for space applications
Experience thriving in fast-paced, high-ownership environments with rapid iteration cycles
Experience with server platforms, AI infrastructure, or high-performance compute systems.
Familiarity with PCIe initialization and accelerator bring-up.
Experience with remote management and fleet-scale telemetry systems.
Knowledge of secure boot, attestation, and firmware security architectures.
Familiarity with radiation-tolerant or fault-resilient system design.

Responsibilities

Design, implement, and verify RTL in SystemVerilog/Verilog for the compute payload's FPGA subsystems, from architecture through on-orbit operation
Develop high-speed camera sensor interfaces, including sensor clocking, configuration, register read/write control, and deterministic pixel capture pipelines
Architect and implement high-throughput datapaths moving pixel data into DDR memory via DMA, with attention to bandwidth, latency, and determinism
Build memory-mapped register interfaces (AXI) between FPGA logic and embedded Linux running on ARM cores, and define the hardware/software contract with flight software engineers
Own timing closure, synthesis, and implementation across Zynq UltraScale+, Versal, and Cyclone 10 targets using Vivado and related toolchains
Develop testbenches and simulation environments to verify designs before hardware, and validate on the bench with logic analyzers, oscilloscopes, and protocol analyzers
Support Petalinux platform bring-up, device tree configuration, and driver-level integration of FPGA peripherals with the embedded Linux stack
Lead board bring-up and hardware integration for new payload avionics, working closely with electrical and embedded software engineers
Investigate anomalies spanning the sensor-to-software chain, perform root cause analysis, and drive fixes across hardware/firmware/software boundaries
Document designs and interfaces, and pair with teammates to spread ownership of the FPGA function across the team
Contribute to build automation, regression testing, and CI for FPGA development workflows
Develop and maintain platform firmware and board management infrastructure for advanced compute systems.
Own system bring-up and low-level boot sequencing for custom hardware platforms.
Design and implement FPGA/CPLD logic for power sequencing, reset orchestration, watchdog functionality, and telemetry.
Develop and customize BMC firmware and management stacks using OpenBMC and related technologies.
Implement and maintain platform management interfaces including Redfish and/or IPMI.
Debug complex hardware/firmware interactions across CPUs, GPUs, PCIe fabrics, and networking devices.
Collaborate closely with hardware, validation, thermal, and systems teams during bring-up and deployment.
Develop fault recovery and autonomous reboot for remote orbital systems.
Support secure boot, firmware update, and system attestation architectures.