FPGA Engineer

York Spaces Systems•Greenwood Village, CO

22h

About The Position

We are seeking an FPGA Engineer to join Yorks Avionics and Payload Engineering team. The successful candidate will be a creative problem solver and life-long learner who continually seeks a deeper understanding and expertise of digital logic design. They must be attentive to detail and disciplined at documentation to ensure quality and maintainability in our products York is a young and growing company that provides fantastic opportunity for ambitious talent to help form the processes, culture, and technical direction of the company.

Requirements

B.S. or M.S. in Electrical and/or Computer Engineering.
Ability to thrive in a collaborative “small-team” culture and environment.
Excellent communication and interpersonal skills, including a demonstrated ability to interact with customers, management, and peers.
Knowledge and deep understanding of RTL coding using Hardware Description Languages (HDL), simulation and FPGA implementation.
Experience with FPGAs, ICs, and tools like Xilinx Design suite, Vivado Chipscope, or Quartus SignalTap.
Experience with SystemVerilog Object-Oriented Programming.
Design experience including design, debug, documentation, and review of RTL design blocks, including an understanding of reset and clocking architecture design.
Ability to debug and validate designs with use of lab tools such as oscilloscopes and logic analyzers.

Nice To Haves

Python, TCL, Make, and shell scripting.
Experience using ModelSim and/or QuestaSim.
Experience with UVM, Assertions, and Constrained Random Verification techniques.
Prior experience working with AMBA Protocols such as AXI or APB.
Develop and maintain an automated regression test environment.
Ability to analyze signal timing characteristics and formulate design constraints.
Knowledge of design techniques for radiation upset mitigation.
Experience developing signal processing algorithms such as filters, (de)modulators, linear recursive sequence generators, correlators, phase-locked loops, error detection and correction encoders/decoders, timing & synchronization, framing/de-framing, packetization, etc.