FPGA Engineer Engineer (eInfochips)

Arrow•San Jose, CA

2d•Onsite

About The Position

eInfochips, an Arrow company (Fortune#154), is a leading global provider of product engineering and semiconductor design services. A rich history of over two decades, with over 500+ products developed and 40M deployments in 140 countries, eInfochips continues to fuel technological innovations in multiple verticals. eInfochips has strategic technology partnerships with Qualcomm, NVIDIA, NXP, Analog Devices, Texas Instruments, Amazon, Microsoft and Google to name a few. Along with Arrow’s $38B in revenues, 22,000 employees, and 345 locations serving over 80 countries, eInfochips is primed to accelerate connected products innovation for 150,000+ global clients. eInfochips acts as a catalyst to Arrow’s Sensor-to-Sunset initiative and offers complete edge-to-cloud capabilities for its clients.

Requirements

9+ Years of experience
Proficient in Verilog/System Verilog coding constructs.
Knowledge of front-end tools (Verilog simulators, Connectivity tools, CDC checkers, low power static checkers, linting)
Experience with high speed PCIe designs and protocols.
Experience with Industry standard interface protocols such as AXI, APB, etc.
Experience with ARM Fabric IPs.
Experience with IPXACT.
Understanding of Computer Architecture fundamentals.
Ability to write scripts using Python, Tcl, Perl etc.
Experience in EDA tools such as VCS, VCLP, Spyglass Lint, Questa CDC, Fusion Compiler, Design Compiler, Genus.
Proficiency with UPF (Low power intent)
Proficiency in clock crossing techniques.
Knowledge of Static Timing Analysis and understanding of timing signoff fundamentals.
Good in understanding RTL Design and Digital concepts
Strong experience with EDA tools: Fusion Compiler, CDC
Scripting: Pearl, Python, TCL
At-least 5+ years of experience in Verilog Design
AMBA AXI bus along-with ARM or C based processor

Responsibilities

Proficient in Verilog/System Verilog coding constructs.
Knowledge of front-end tools (Verilog simulators, Connectivity tools, CDC checkers, low power static checkers, linting)
Experience with high speed PCIe designs and protocols.
Experience with Industry standard interface protocols such as AXI, APB, etc.
Experience with ARM Fabric IPs.
Experience with IPXACT.
Understanding of Computer Architecture fundamentals.
Ability to write scripts using Python, Tcl, Perl etc.
Experience in EDA tools such as VCS, VCLP, Spyglass Lint, Questa CDC, Fusion Compiler, Design Compiler, Genus.
Proficiency with UPF (Low power intent)
Proficiency in clock crossing techniques.
Knowledge of Static Timing Analysis and understanding of timing signoff fundamentals.
Good in understanding RTL Design and Digital concepts
Strong experience with EDA tools: Fusion Compiler, CDC
Scripting: Pearl, Python, TCL
At-least 5+ years of experience in Verilog Design
AMBA AXI bus along-with ARM or C based processor
Ensure customer satisfaction.
Reporting to customers on daily or weekly progress effectively