FPGA Engineer II

RTX•Plano, TX

1d•$68,900 - $131,100•Onsite

About The Position

At Raytheon, the foundation of everything we do is rooted in our values and a higher calling – to help our nation and allies defend freedoms and deter aggression. We bring the strength of more than 100 years of experience and renowned engineering expertise to meet the needs of today’s mission and stay ahead of tomorrow’s threat. Our team solves tough, meaningful problems that create a safer, more secure world. In this role as an FPGA Engineer II, you will be supporting a development program within the Airborne RF Electronics Design Department. You will develop FPGA designs for all major vendors and device families including AMD, Altera, and Microchip. Designs commonly support the following applications: multi-gigabit interfaces, Radio Frequency (RF) and Electro-Optical (EO) DSP, controls, data links, embedded processing, and processor interfaces. Designers collaborate with circuit card designers and systems engineers to develop requirements, architecture, modeling of algorithms, partitioning, code development, simulation, and place and route. Designs are verified against requirements using both directed tests and constrained random methodologies. Design support is expected from requirements definition through production release. Design documentation and configuration management are required. This position is an onsite role, located in Plano, TX.

Requirements

Typically requires a degree in Science, Technology, Engineering or Mathematics (STEM) and a minimum of 2 years of prior relevant experience.
Experience to include at least 4 of the following:
FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Experience with AMD (Xilinx), Altera and/or Microchip (Microsemi) devices and with tools such as AMD Vivado, Altera Quartus Prime Pro or Libero.
Hands-on experience with integration and debug of FPGA/ASIC in a lab environment
Experience with Git source code management, design reviews, and code release in a team development environment.
Experience with Python or C programming
Experience with CI/CD pipelines
Experience with digital simulation such as Questa, RivieraPro or similar tools
The ability to obtain and maintain a U.S. government issued security clearance post-start is required. U.S. citizenship is required, as only U.S. citizens are eligible for a security clearance.

Nice To Haves

One or more advanced degrees in Electrical Engineering or a related Science, Technology, Engineering, or Mathematics (STEM) major. A suitable degree may be counted as 2 years of work experience.
FPGA/ASIC design experience in one or more of the following areas:
Embedded systems design using ARM, Microblaze, or NIOS processors
Gigabit serial interfaces and multi-gigabit transceivers (MGTs)
Constrained random verification in UVM using System Verilog
Experience with High Level Synthesis (HLS)
Experience with vector processors and/or GPUs
Experience with timing closure, clock domain crossing and reset domain crossing analysis, and constraint development.
Demonstrated ability to lead design efforts and/or small teams.
Familiarity with AI LLM assisted workflows
Knowledge of encryption/decryption standards such as AES, RSA, ECC, etc.

Responsibilities

Provide full lifecycle support of production quality FPGA designs for one or more major vendors and device families including: AMD (Xilinx), Altera, and Microchip (Microsemi).
Generate FPGA designs for the following applications: multi-gigabit serial interfaces, Radio Frequency (RF) DSP, controls, data links, embedded processing and processor interfaces.
Assist with architecture development of FPGA-based systems to determine parts, interfaces, and Concept of Operations (CONOPS).
Design and code in VHDL for reliability and maintainability.
Support design verification utilizing self-checking techniques with directed and constrained random tests, while tracking functional and code coverage.
Understand and report execution status to the planned budget and schedule using an agile framework.
Create complete documentation including requirements, verification plan, and user’s guides.
Function as an individual contributor.
Clearly present your work product to leadership.
Engage in professional growth and development.