Full Time Raytheon 2026 - Multi-Product Power & Digital FPGA Engineer II

RTXFort Wayne, IN
$68,900 - $131,100Onsite

About The Position

The Multi-Product Power & Digital department is seeking an FPGA (Field Programmable Gate Array) Engineer II to join our team. This FPGA Engineer is responsible for FPGA and hardware designs for electronic warfare, radar, and effector products. Job responsibilities of this role include activities such as troubleshooting electronics in a lab or production environment, performing system and circuit level analysis, supporting failure investigations, maintaining and creating documentation, hardware and/or logic design, and interacting with multi-discipline groups including suppliers.

Requirements

  • Masters’s degree in Electrical Engineering, Computer Engineering or related Science, Technology, Engineering, or Mathematics (STEM) major.
  • Experience to include one or more of the following: FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
  • Experience with AMD (Xilinx), Altera and/or Microchip (Microsemi) devices and with tools such as AMD Vivado, Altera Quartus Prime Pro or Libero.
  • Hands-on experience with integration and debug of FPGA/ASIC in a lab environment
  • Experience with source code management, design reviews, and code release in a team development environment.
  • The ability to obtain and maintain a U.S. government issued security clearance is required.
  • U.S. citizenship is required, as only U.S. citizens are eligible for a security clearance.

Nice To Haves

  • 3.0 cumulative GPA desired from an ABET accredited institution.
  • Demonstrated experience with VHDL or Verilog coding, simulation, and synthesis.
  • Knowledge of electrical circuit design, analysis and troubleshooting using common lab equipment.
  • FPGA/ASIC design experience in one or more of the following areas: Embedded systems design using ARM, Microblaze, or NIOS processors
  • Gigabit serial interfaces and multi-gigabit transceivers (MGTs)
  • Constrained random verification in UVM using System Verilog
  • Experience with High Level Synthesis (HLS)
  • Experience with vector processors and/or GPUs
  • Experience with timing closure, clock domain crossing and reset domain crossing analysis, and constraint development.
  • Demonstrated ability to lead design efforts and/or small teams.

Responsibilities

  • Work onsite at our Fort Wayne, IN Location
  • Provide Full Lifecycle support of production quality FPGA
  • Generate FPGA Designs
  • Design and Code in VHDL for reliability and maintainability
  • Create complete documentation including requirements, verification plan, and users guides

Benefits

  • Relocation Assistance
  • medical
  • dental
  • vision
  • life insurance
  • short-term disability
  • long-term disability
  • 401(k) match
  • flexible spending accounts
  • flexible work schedules
  • employee assistance program
  • Employee Scholar Program
  • parental leave
  • paid time off
  • holidays
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