FPGA Design Engineer - DSP & High-Speed Data Systems

Knowmadics, Inc•Wichita, KS

9d•Hybrid

About The Position

The FPGA Design Engineer supports the rapid development of next-generation, AI-enabled hardware and sensor platforms for counter-UAS (cUAS) and multi-sensor applications. This role helps build the programmable-logic and DSP capabilities that connect custom hardware to the rest of the system. The engineer will implement, simulate, integrate, and debug FPGA logic for high-speed data movement, RF signal processing, sensor interfaces, control/status registers, and software-facing data paths. This includes working with HDL, AXI/AXI-Stream, clocks, resets, CDC, DMA-facing interfaces, and hands-on hardware validation. Working closely with the FPGA systems lead, electrical, embedded software, RF, DSP, mechanical, and application software engineers, this role helps turn new hardware concepts into modular, mission-ready capabilities. The ideal candidate will be excited to work in a fast-moving R&D environment, learn quickly, solve hands-on FPGA integration problems, and help build technology that moves quickly from concept to real-world impact.

Requirements

Eligible to obtain a U.S. Security Clearance - U.S. Citizenship required.
B.S. in Electrical Engineering, Computer Engineering, Computer Science, or related technical field, or equivalent practical experience.
3+ years of FPGA design experience with VHDL, Verilog, or SystemVerilog, including simulation, implementation, and hands-on hardware debug.
Experience with AMD/Xilinx, Intel/Altera, Lattice, or similar FPGA platforms.
Working understanding of synchronous digital design, timing closure, clock domains, resets, FIFOs, CDC, and FPGA implementation flow.
Experience integrating FPGA logic into real hardware and debugging issues in the lab.
Working knowledge of streaming data paths, register-mapped control, interrupts, and software-controlled FPGA systems.
Ability to collaborate with electrical, embedded software, RF, DSP, and systems engineers to implement clean hardware/software interfaces.
Clear communicator who can document interfaces, assumptions, constraints, and test results.

Nice To Haves

5+ years of FPGA experience with DSP, RF signal processing, AXI/AXI-Stream, JESD204, high-speed data movement, or software-controlled FPGA systems.
Experience with FPGA-based DSP, SDR, radar, communications, electronic warfare, cUAS, or distributed sensor systems.
Experience with AXI/AXI-Stream, DMA-oriented interfaces, PCIe, Ethernet, JESD204, ADC/DAC integration, or high-speed transceivers.
Experience with MATLAB, Python, C/C++, or similar tools for modeling, test automation, data analysis, or hardware control.
Experience creating register maps, command/control interfaces, or utilities used by software teams.
Experience with embedded processors, SoCs, soft processors, or mixed FPGA/software systems.
Comfort reading schematics, datasheets, timing diagrams, and board-level interface specifications.
Active DoD clearance or prior clearance eligibility.

Responsibilities

Implement FPGA logic for DSP, RF data movement, sensor interfaces, control paths, and high-speed streaming or packetized data systems.
Develop RTL in VHDL, Verilog, or SystemVerilog and support simulation, synthesis, implementation, and timing closure.
Build and debug AXI, AXI-Stream, FIFO, register, interrupt, clocking, reset, CDC, and DMA-facing interfaces under technical guidance.
Support integration of ADC/DAC, JESD204, Ethernet, PCIe-facing, transceiver, or other high-speed interfaces as project needs require.
Create and maintain software-friendly register maps, control/status interfaces, debug hooks, test modes, and bring-up notes.
Collaborate with embedded software engineers on register access, interrupts, data formats, buffer behavior, throughput, and latency goals.
Collaborate with electrical engineers during board bring-up, signal validation, clock/reset debug, and hardware troubleshooting.
Use FPGA debug tools such as ILA, SignalTap, timing reports, simulations, and lab equipment to isolate and solve issues.
Support rapid prototypes, bench tests, field demonstrations, and iterative design updates in a fast-moving R&D environment.
Document design intent, interfaces, constraints, test results, and known limitations clearly enough for team reuse.