FPGA Compiler (Placer) Engineer

Altera Semiconductor•San Jose, CA

6d•Onsite

About The Position

Altera is a leader in FPGA innovation, delivering programmable solutions that power AI, cloud computing, networking, and edge applications. Our compiler and tools teams are central to enabling customers to efficiently map complex designs onto advanced FPGA architectures. Altera is seeking a FPGA Compiler Engineer (Placer) to join our Compiler team in San Jose, CA. This role focuses on developing and optimizing FPGA placement algorithms within the compiler toolchain, directly impacting performance, power efficiency, and overall design quality. The ideal candidate brings strong expertise in EDA algorithms, large-scale system optimization, and FPGA/ASIC physical design flows, along with a passion for solving complex, performance-critical problems.

Requirements

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
6+ years of experience in FPGA/ASIC CAD, EDA tools, or related fields.
Experience in algorithms and data structures (optimization, graph theory, heuristics)
Experience with placement algorithms or physical design flows
Experience in C/C++ and software engineering best practices
Experience with placement techniques (analytical placement, simulated annealing, partitioning, clustering)
Experience with Timing-driven and congestion-driven optimization
Experience in ASIC or FPGA physical design methodologies
Experience in solving complex, large-scale optimization problems with high performance and scalability requirements.
Applicants must be eligible for any required U.S. export authorizations.

Nice To Haves

Experience with FPGA toolchains (e.g., Quartus, Vivado )
Knowledge of FPGA architectures and interconnect fabrics
Familiarity with routing and timing closure techniques
Experience with parallel or distributed algorithms for EDA tools
Scripting experience (e.g., Python, Tcl ) for tooling and automation

Responsibilities

Design, implement, and enhance FPGA placement algorithms to optimize timing, congestion, and resource utilization.
Contribute to the end-to-end FPGA compilation flow, working closely with routing, synthesis, and timing teams.
Improve runtime performance, scalability, and quality of results (QoR) for large and complex customer designs.
Develop and refine timing-aware placement strategies to support high-frequency, performance-critical designs.
Partner with architecture, routing, and STA teams to align placement strategies with FPGA device capabilities and constraints.
Analyze placement quality, congestion hotspots, and timing bottlenecks; drive improvements to convergence and design closure.
Integrate new placement capabilities into the compiler infrastructure and validate across diverse workloads.