FPGA/ASIC Design & Analysis Engineer Level 5

Indotronix International CorporationEl Segundo, CA
Onsite

About The Position

Indotronix is seeking an FPGA/ASIC Design & Analysis Engineer Level 5 for an onsite position in El Segundo, CA. The role involves first shift work from 8:00 AM to 4:30 PM, with possible overtime opportunities. An active Secret Clearance is required to start.

Requirements

  • 5+ years of FPGA and/or ASIC design experience
  • strong Xilinx/AMD Vivado experience
  • Experience with Versal family devices
  • Verilog/SystemVerilog HDL proficiency required
  • Advanced FPGA implementation skills (synthesis, timing closure, constraints)
  • Active U.S. security clearance

Nice To Haves

  • 2+ years of FPGA design experience
  • strong Xilinx/AMD Vivado experience
  • Verilog/SystemVerilog proficiency
  • Advanced FPGA implementation skills (synthesis, timing closure, constraints)

Responsibilities

  • Demonstrate strong digital hardware fundamentals.
  • Exercise sound engineering judgment.
  • Work independently with minimal oversight.
  • Communicate clearly and proactively.
  • Produce high-quality technical documentation.
  • Take ownership of their work and deliver maintainable engineering solutions.
  • Clearly explain personal technical contributions, design decisions, debugging approach, and ownership of deliverables.
© 2026 Teal Labs, Inc
Privacy PolicyTerms of Service