FPGA AI/ML Engineer (part time)
Riverside Research Institute•Fairborn, OH
•Onsite
About The Position
Riverside Research is seeking a part-time or full-time FPGA developer with expertise in Vivado, Vitis, VHDL, and Verilog. As a valued Riverside Research employee, you will be part of a highly skilled and integrated team that develops automation solutions to challenging Scientific & Technical problems. Because this role requires regular local engagement and collaboration, we are exclusively considering candidates who currently reside in the greater Dayton, Ohio area. All Riverside Research opportunities require U.S. Citizenship.
Requirements
- Bachelors’ degree in either Computer Engineering, Electrical Engineering, Mathematics, Statistics, Physics, Computer Science, or related field of study
- Ability to troubleshoot digital logic and electronic breadboard designs
- Twelve years’ experience with FPGA development
- Five years’ experience with Vivado / Vitis software
- Two years’ with a high-level language such as Python or Matlab
- Proficient in collaborative Office 365 tools such as MS Word, Excel, and PowerPoint
- Ability to work closely with subject-matter experts to develop tools, algorithms, and datasets needed for developing relevant and useful AI/ML prototype algorithms
- Self-driven, strong analytic, inferencing, critical thinking, and creative problem-solving skills
- Communicates highly technical results and methods clearly and succinctly
- U.S. Citizenship
Nice To Haves
- TS/SCI Clearance
- Advanced degree (MS/PhD) in Data Science, Mathematics, Statistics, Computer Science, a Physical Science or Engineering
- Experience with AI/ML, Computer Vision, and Image Processing Techniques
- Experience with DoD and Intelligence Community customers
Responsibilities
- Design, implement, and optimize FPGA video and image processing solutions using AMD/Xilinx toolchains (Vivado, Vitis) using VHDL, Verilog, or HLS.
- Integrate FPGA designs into larger systems, ensuring robust verification, documentation, and deployment across multiple platforms (UltraScale, Versal).
- Develop end to end unit and black box testing to measure system performance and support verification & validation.
- Support the transition of AI/ML Python, C/C++, and Matlab Algorithms to FPGA designs.
Benefits
- comprehensive compensation and benefit packages
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What This Job Offers
Job Type
Full-time
Career Level
Senior
