Formal Verification Engineer - CPU Core

Intel Corporation•Folsom, CA

4d•$105,650 - $200,340•Hybrid

About The Position

Intel is shaping the future of technology to help create a better future for the entire world. Our work in pushing forward fields like AI, analytics, and cloud-to-edge technology is at the heart of countless innovations. With a career at Intel, you'll have the opportunity to use technology to power major breakthroughs and create enhancements that improve our everyday quality of life. Join us and help make the future more wonderful for everyone. Life at Intel We're looking for a motivated and talented engineer to join the US CPU verification team. In this role you will be critical to the development of next generation CPU's designed to power the AI revolution. You will join the team responsible for exhaustively verifying the architecture and micro-architecture changes implemented in the CPU using a combination of dynamic and formal verification methods. Job responsibilities include writing verification test plans, and then writing tests to execute those plans. Development of pre-silicon verification collateral (such as behavioral checkers, coverage monitors, test generators or score-boards) is often required to enable test plan execution. On Formal front, responsibilities may include technical ownership of formal verification of a microarchitecture block, methodology, or otherwise significant aspect of the Big Core CPU, Understand and contribute to micro-architecture specification and define the formal verification strategy for a significant portion of the design, Lead ROI analysis and recommend appropriate use of formal verification vs dynamic validation techniques for relevant parts of the CPU. Candidates will need to debug failing tests, then work with designers and architects to resolve bugs. Successful verification engineers can anticipate failure modes, and write punishing test content to stress the design and identify bugs. Candidate will analyze coverage gaps and devise strategies to fill coverage holes. The quality of the design and the final product is directly proportional to the quality of the design verification work. The job involves working with Global RTL, Arch DV and Formal teams to define verification strategy, planning and execution, driving verification methodologies etc. Behavioral traits for this position include: - Strong problem solving - Tolerance of ambiguity

Requirements

Bachelors degree in Computer Engineering or Electrical Engineering or related STEM field and 2+ years of relevant work experience OR a Masters degree in Computer Engineering or Electrical Engineering or related STEM field and 1 year of relevant work experience.
1+ years’ experience in/with: In-depth computer architecture knowledge with emphasis on out of order processor execution, memory hierarchy, and memory management
1+ years’ experience in/with: Hardware modeling language, such as Verilog, VHDL, or System Verilog and industry standard logic simulation tools
1+ years’ experience in/with: Assertion writing, checker development, coverage analysis, failure debug, root cause analysis
1+ years’ experience in/with: Programming in at least one language: C/C++, Java, Specman E etc. and familiarity with any of scripting languages: Perl, Python, Ruby, TCL
1+ years’ experience in/with: Intel or industry experience in pre-silicon verification of CPU cores, including specific areas of technical ownership/expertise relevant to CPUs
1+ years’ experience in/with: Industry standard formal verification tools such as JasperGold, IFV, Questa Formal, VC Formal

Nice To Haves

Knowledge of Intel Architecture ISA and system architecture, x86 assembly language.
Pre/Post-silicon debug and analysis
Research publications, patent filings, or other evidence of personal technical innovation in validation methodology advancement.
Applying sequential equivalence checking in complex micro-architectures
Formal abstractions and other complexity reduction techniques

Responsibilities

Writing verification test plans, and then writing tests to execute those plans.
Development of pre-silicon verification collateral (such as behavioral checkers, coverage monitors, test generators or score-boards) is often required to enable test plan execution.
Technical ownership of formal verification of a microarchitecture block, methodology, or otherwise significant aspect of the Big Core CPU.
Understand and contribute to micro-architecture specification and define the formal verification strategy for a significant portion of the design.
Lead ROI analysis and recommend appropriate use of formal verification vs dynamic validation techniques for relevant parts of the CPU.
Debug failing tests, then work with designers and architects to resolve bugs.
Anticipate failure modes, and write punishing test content to stress the design and identify bugs.
Analyze coverage gaps and devise strategies to fill coverage holes.
Working with Global RTL, Arch DV and Formal teams to define verification strategy, planning and execution, driving verification methodologies etc.