Firmware Engineer

ICEYE US•Irvine, CA

5d•$145,000 - $175,000•Onsite

About The Position

At ICEYE, we design, build and operate the largest fleet of Synthetic Aperture Radar (SAR) satellites in the world. Using advanced technology, our constellation collects topographical data about any location on Earth, day or night, through any weather conditions. Headquartered in Southern California, our customers are society’s heroes – intelligence professionals, warfighters, first responders, and scientific researchers. As a trusted mission partner, the United States and its allies depend on us for critical information when it matters most. Role Description The Firmware Engineer will be a core member of the Space Systems engineering team, responsible for designing, developing, and verifying firmware for radar and synthetic aperture radar (SAR) payload electronics. This role directly supports product iterations by owning the FPGA architecture for signal generation, digital signal processing, and hardware-software interfaces within the payload avionics chain. The engineer will work closely with RF, systems, embedded software, and AIT engineers to deliver flight-quality firmware.

Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master's preferred)
5-8 years of professional experience designing FPGA firmware in VHDL and/or Verilog
3+ years of experience with Xilinx (AMD) development tools (Vivado, Vitis, Vivado HLS)
At least 3-5 years demonstrated experience with digital signal processing implementation in FPGA fabric (filtering, FFTs, digital down-conversion, waveform generation)
3-5 years hands-on experience developing firmware for System-on-Chip (SoC) architectures, including PS–PL integration on Zynq or Zynq UltraScale+ platforms
Working knowledge of high-speed serial interfaces and standard bus protocols.

Nice To Haves

Experience with Xilinx RFSoC devices (ZU27DR, ZU47DR, or similar), including direct RF sampling ADC/DAC integration
Background in radar or SAR signal processing (pulse compression, range/Doppler processing, beamforming algorithms)
Familiarity with radar waveform design and RF system-level concepts (noise figure, dynamic range, spurious analysis)
Experience in aerospace, defense, or space-qualified hardware development environments
Exposure to formal verification methodologies (UVM, constrained-random testbenches, code coverage analysis)
Experience with embedded Linux and bare-metal firmware development on ARM Cortex-A/R processors within SoC platforms
Familiarity with configuration management practices and version-controlled FPGA release workflows (Git, CI/CD for HDL)
Knowledge of environmental qualification and reliability considerations for FPGA designs (radiation effects, thermal derating, FMEA contributions)
Experience supporting hardware integration and test campaigns, including bench-level debug with oscilloscopes, logic analyzers, and spectrum analyzers

Responsibilities

Design, implement, and verify FPGA firmware for radar signal generation, digital beamforming, and SAR data processing pipelines
Develop and maintain RTL (VHDL/Verilog) targeting Xilinx RFSoC and UltraScale+ platforms
Architect a modular, reusable FPGA framework that supports multiple product configurations and minimizes NRE for future payload variants
Integrate FPGA firmware with embedded software (Linux/bare-metal) running on SoC processing systems (ARM cores)
Define and implement high-speed digital interfaces between FPGA fabric and RF/analog front-end hardware.
Perform timing closure, resource optimization, and power analysis for flight-grade FPGA builds
Develop and execute FPGA verification strategies including simulation, hardware-in-the-loop testing, and integration with flat-sat and EGSE test environments
Collaborate with RF and systems engineers to translate radar waveform and signal processing requirements into FPGA design specifications
Support AIT activities by providing firmware builds, diagnostic modes, and debug support during payload integration and test campaigns
Create and maintain configuration-managed firmware baselines, release documentation, and design descriptions aligned with gated review processes (PDR/CDR/TRR)
Participate in design reviews, trade studies, and technical risk assessments related to FPGA and digital subsystem architecture