Fellow Architect, Functional & Performance Verification

Advanced Micro Devices, Inc•San Jose, CA

8d•Hybrid

About The Position

ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them. AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward. THE ROLE: We are looking for a visionary Fellow-level Functional and Performance Verification/Validation Architect to lead the evolution of AMD’s pre-silicon verification and validation strategy within the Adaptive and Embedded Computing Group (AECG). In this role, you will shape next-generation verification architectures, methodologies, and technologies spanning IP, subsystem, and SoC development. By combining deep domain expertise with advanced verification techniques, ML/AI innovations, industry-standard protocols, and leading EDA solutions, you will drive transformational improvements in verification quality, efficiency, and scalability. Your leadership will be instrumental in enabling first-pass silicon success and meeting the demands of increasingly complex designs and aggressive product schedules. THE PERSON: As a Fellow-level Functional and Performance Verification Architect, you will lead the definition and advancement of next-generation verification methodologies, technologies, and best practices. You will act as a catalyst for innovation, identifying opportunities to improve verification effectiveness, scalability, and productivity while driving adoption across the organization. The role demands exceptional technical depth, strategic vision, and the ability to influence without authority. You will work closely with engineering leadership, architects, design teams, and EDA partners to develop and deploy innovative solutions that address the challenges of increasingly complex semiconductor designs.

Requirements

Expert in programming and scripting languages such as C/C++, Python, Perl, and Ruby, along with strong proficiency in HDL/Verilog and UVM-based verification methodologies.
Deep background in architecting, developing, and deploying advanced functional verification and validation methodologies, frameworks, and environments for complex semiconductor designs.
Hands-on experience with pre-silicon prototyping and emulation platforms and their application to functional and performance verification.
Self-motivated technical leader with a demonstrated ability to identify innovation opportunities, define new methodologies, and drive initiatives from concept through successful deployment.
Expert understanding of functional and performance verification tools, technologies, and solutions offered by leading EDA vendors. (Synopsys, Cadence Design, Siemens)
Strong analytical and problem-solving capabilities, with a rigorous attention to detail and a passion for tackling complex technical challenges.
Proven ability to collaborate effectively across diverse engineering disciplines, organizations, and global teams while delivering high-quality results on schedule.
Established record of technical thought leadership through publications, technical papers, patents, and presentations at internal and external conferences.

Responsibilities

Drive the definition, development, and execution of industry-leading functional and performance verification and validation strategies, encompassing verification planning, testbench architecture, development of verification collaterals, debug methodologies, and coverage closure across IP, subsystem, and SoC programs within AECG and AMD.
Lead the evolution of simulation-based verification methodologies, encompassing constrained-random, directed, and coverage-driven approaches, while advancing formal, power, performance, and implementation verification strategies across AECG and AMD.
Lead the advancement of simulation-based verification methodologies—including constrained-random, directed, and coverage-driven techniques—while enhancing formal, power, performance, and implementation verification capabilities across the verification organization.
Lead the evolution of firmware-based validation strategies and methodologies across prototyping and emulation platforms, accelerating verification convergence and silicon readiness.
Influence and shape the evolution of verification methodologies by working closely with AECG executives and senior leaders to address the needs of current and future silicon programs.
Work closely with architecture, design, and verification leaders to identify emerging challenges, align on requirements, and develop scalable verification methodologies that improve quality, efficiency, and predictability across future products.
Influence architectural and design decisions by partnering with architecture and RTL teams to embed “First-Time-Right” and Design-for-Verification principles into next-generation products.
Establish and lead strategic engagements with EDA vendors to influence product roadmaps, enhance existing capabilities, and develop next-generation verification methodologies and tools.
Serve as a technical mentor and trusted advisor to verification engineers across AECG, elevating organizational expertise through coaching, knowledge sharing, and thought leadership.
Contribute to AMD’s technical leadership and industry presence through publications, technical papers, and presentations at both internal and external conferences.