Engineering Manager, Wireless and Digital Design

Hubble Network•Seattle, WA

13d•$169,600 - $266,000•Onsite

About The Position

Hubble Network is building a global Bluetooth® network for machine-to-machine connectivity, aiming to be the first billion-endpoint-connected network. This role is for an Engineering Manager, Wireless & Digital Design to lead the design and implementation of Hubble's wireless communication and localization systems on satellite FPGAs. This is a player-coach role where the individual will bring senior-level wireless systems expertise and manage a team of digital design engineers. The responsibilities include defining algorithms and protocols for connecting terrestrial Bluetooth devices to satellites and determining their position, and directing the digital design team responsible for the RTL codebase for localization and decoding BLE transmissions. The role involves close collaboration with leaders across hardware, firmware, software, and customer success to translate strategic goals into product plans. It is a hands-on role for a builder who can engage with technical details, customer insights, and company strategy.

Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
10+ years of experience across wireless systems and/or FPGA-based digital design.
3+ years leading or managing engineering teams.
Strong understanding of communication theory and digital signal processing (DSP) — filtering, correlation, decimation, channel estimation, beamforming, timing recovery, coding/error correction, and fixed-point arithmetic.
Experience with Matlab or Python and/or C/C++ for algorithm development, modeling, and simulation.
Experience with simulation/verification tools (e.g., ModelSim, Questa, Vivado) and scripting (Python, Tcl).
Experience developing packet decoders for wireless communication protocols (e.g., BLE, ZigBee, LoRa, or custom PHYs).
Experience designing localization or geolocation algorithms (e.g., Doppler-based positioning, TDOA/FDOA, angle-of-arrival, or Kalman/particle filtering for position estimation).
Proven expertise overseeing RTL design (Verilog/SystemVerilog) for high-throughput, low-latency digital receivers.
Skilled in FPGA synthesis, timing closure, and resource optimization on Xilinx or Intel/Altera platforms.
Familiarity with high-speed memory interfaces (DDR/DDR3/DDR4) and high-speed serial interfaces (LVDS, SPI, I2C, UART, SERDES-based links such as JESD204, PCIe, Ethernet).
Demonstrated ability to lead technical teams: setting direction, mentoring engineers, running design reviews, and delivering against evolving requirements.
Ability to work closely with RF engineers, firmware developers, and systems engineers to integrate and validate end-to-end communication chains.
Strong interpersonal, verbal, and written communication skills.
Ability and willingness to thrive in a fast-paced, rapidly changing work environment.
Must be a U.S. citizen, lawful permanent resident (“green card holder”) as defined by ITAR (22 CFR §120.15).

Nice To Haves

+15 years of directly relevant experience
Prior experience managing digital design or FPGA teams
Experience with satellite-based geolocation or positioning systems (e.g., Doppler geolocation from LEO)
Experience designing distributed digital signal processing systems across multiple FPGAs or compute nodes
Familiarity with soft-core or hard-core processor integration (e.g., ARM) and peripheral interfacing (SPI, I2C, AXI); embedded Linux (Petalinux) experience
Familiarity with synchronization techniques (preamble detection, symbol timing recovery, frequency offset correction)
Multi-radio coexistence management
Experience with lab tools such as oscilloscopes, logic analyzers, and RF test equipment for bring-up and debugging
Knowledge of low-power design techniques for space-based or resource-constrained systems

Responsibilities

Lead the design of Hubble's wireless communication and localization systems.
Own the implementation of these systems in HDL on satellite FPGAs.
Model, design algorithms, and architect systems for direct-to-satellite Bluetooth connectivity and geolocation.
Manage and grow the team of digital design engineers responsible for FPGA implementations.
Define the algorithms and protocols that connect terrestrial Bluetooth devices to satellites and determine their position from orbit.
Direct the digital design team responsible for the RTL codebase that performs localization and decodes packets from ground-based BLE transmissions.
Work closely with leaders across hardware, firmware, software, and customer success to translate strategic goals into clear product plans and deliverables.
Oversee RTL design (Verilog/SystemVerilog) for high-throughput, low-latency digital receivers.
Lead technical teams, setting direction, mentoring engineers, running design reviews, and delivering against evolving requirements.
Integrate and validate end-to-end communication chains with RF engineers, firmware developers, and systems engineers.