Engineer

Qualcomm • Markham, ON

10d • CA$90,100 - CA$135,100

About The Position

QCT's DSP Physical Design Team is seeking motivated and talented Physical Design Engineer to join our growing team in Markham, Canada. In this role, you will contribute to the implementation of cutting-edge DSP cores used in next-generation mobile, compute, and AI-enabled products. Working alongside experienced engineers, you will gain hands-on exposure to the complete ASIC development cycle, from RTL handoff through physical implementation and tapeout.
This position is ideal for early-career engineers with a strong foundation in VLSI and digital design fundamentals who are passionate about semiconductor technology and eager to build expertise in Physical Design, timing closure, power optimization, and silicon realization. You will collaborate closely with architecture, RTL, verification, DFT, and methodology teams while learning industry-leading design flows, automation techniques, and advanced implementation methodologies.
The role offers excellent opportunities for technical growth, mentorship, and career development while working on complex and high-impact designs in a fast-paced, innovation-driven environment. Candidates with strong engineering fundamentals, problem-solving abilities, and a willingness to learn new technologies will thrive in this position.

Requirements

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• 6 months to 2 years of experience in ASIC Physical Design, Digital Design, VLSI, or a related semiconductor domain (including internships or co-op experience).
• Strong understanding of VLSI and digital design fundamentals, including combinational and sequential logic, FSMs, clocking concepts, and timing analysis.
• Basic understanding of ASIC design flow from RTL to GDSII.
• Familiarity with Physical Design concepts such as floorplanning, placement, CTS, routing, timing analysis, and physical verification.
• Exposure to industry-standard EDA tools used for synthesis, implementation, timing analysis, or verification.
• Basic scripting skills in Python, Tcl, Perl, or Shell.
• Strong analytical, debugging, and problem-solving skills.
• Effective communication and teamwork abilities.

Nice To Haves

• Coursework, academic projects, internship, or industry experience in VLSI, ASIC, Digital Design, or Physical Design.
• Familiarity with Verilog/SystemVerilog, RTL design, synthesis, and verification methodologies.
• Understanding of STA, DFT fundamentals, low-power design concepts, and silicon implementation flows.
• Experience developing automation scripts and productivity tools for engineering workflows.
• Familiarity with data analysis, AI-assisted engineering tools, or emerging AI technologies that enhance engineering productivity.
• Demonstrated curiosity, learning agility, and passion for semiconductor technology.
• Strong ownership mindset and willingness to take on challenging technical problems.

Responsibilities

• Contribute to ASIC Physical Design activities from netlist to GDSII under the guidance of senior engineers.
• Support floorplanning, placement, clock tree synthesis, routing, timing analysis, and physical verification tasks.
• Analyze and debug timing, congestion, and design rule issues.
• Participate in PPA (Power, Performance, Area) analysis and optimization activities.
• Assist with ECO implementation, design closure, and tapeout readiness.
• Collaborate with RTL, DFT, verification, and methodology teams to resolve design and implementation challenges.
• Develop scripts and automation solutions to improve engineering productivity and design quality.
• Learn and apply industry best practices for advanced semiconductor design and implementation.

Benefits

• Competitive annual discretionary bonus program
• Opportunity for annual RSU grants
• Highly competitive benefits package designed to support your success at work, at home, and at play.

What This Job Offers

• Job Type: Full-time
• Career Level: Entry Level