Engineer-Staff

Qualcomm • Austin, TX

6d • $140,000 - $210,000

About The Position

This role involves hands-on experience in Synthesis, Place and Route (PnR), Physical Design, and Timing/Power Signoff. The engineer will have a strong understanding of Physical Synthesis methodologies, Floorplanning, Placement, Clock Tree Synthesis (CTS), and Routing using industry-standard tools. The primary focus is on driving PPA (Power, Performance, Area) activities, including area recovery, power reduction, and performance improvements, while balancing trade-offs across synthesis and physical implementation. Experience with advanced technology nodes and low-power design implementation using UPF is also crucial.

Requirements

• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
• Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
• PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
• Strong understanding and in-depth knowledge of Physical Synthesis, and methodologies, Floorplanning, Placement, Clock Tree Synthesis (CTS), Routing, with leading industry standard tools.
• Hands-on experience on advanced technology nodes, including node-specific challenges around double/multi-patterning, pin access, cell legalization, and advanced DRC rules.
• Experience with writing and tuning timing constraints for synthesis, STA, timing closure, and pipelining at different levels for performance optimization.
• Experience in all aspects of timing closure for multi-clock domain, multi-corner multi-mode (MCMM) designs, both at synthesis and at the physical design stage.
• Good understanding of low-power design implementation using UPF, including power gating, multi-voltage domains, and level shifter/isolation cell placement/routing.
• Experience with different power optimization flows/techniques across synthesis and PD — such as clock gating, cell sizing, Vt swapping, and buffer/inverter insertion/optimization.
• Proficiency in Python/Tcl and AI Usage.
• Familiarity with standard software engineering practices like Version Control, Configuration Management, and Regression.
• Familiar with PnR tools (Innovus/ICC2) and Synthesis tools (Fusion Compiler/Genus).
• Proven hands-on experience on advanced nodes , with awareness of node-specific PPA levers and physical constraints.
• Fair knowledge of Static Timing Analysis (PrimeTime/Tempus), LEC, and Low Power (LP) signoff tools.
• Proficient in VLSI front-end and back-end design steps — Synthesis, QoR optimization, floorplanning, placement, CTS, routing, and Equivalence Checking.
• Strong PPA mindset — comfortable owning power, performance, and area metrics as primary KPIs.

Nice To Haves

• Master's degree in Electrical/Electronic Engineering, Computer Engineering, or Computer Science.
• 6+ years of ASIC design, verification, validation, integration, or related work experience.
• 2+ years of experience with architecture and design tools.
• 2+ years of experience with scripting tools and programming languages.
• 2+ years of experience with design verification methods.
• 1+ year of work experience in a role requiring interaction with senior leadership (e.g., Director level and above).
• Knowledge of computer architecture and experience in high-speed, low-power processor design.

Responsibilities

• Drive end-to-end PPA optimization across the synthesis-to-PnR boundary.
• Implement and optimize designs on advanced technology nodes, addressing node-specific challenges.
• Write and tune timing constraints for synthesis, STA, timing closure, and pipelining.
• Focus on aggressive area recovery, leakage/dynamic power reduction, and Fmax/performance pushes.
• Perform timing closure for multi-clock domain, multi-corner multi-mode (MCMM) designs.
• Implement low-power designs using UPF, including power gating, multi-voltage domains, and level shifter/isolation cell placement/routing.
• Utilize various power optimization flows and techniques across synthesis and PD.

Benefits

• Competitive annual discretionary bonus program
• Opportunity for annual RSU grants
• Highly competitive benefits package designed to support your success at work, at home, and at play.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior